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IxAtmTypes.h

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00001 
00048 /* ------------------------------------------------------
00049    Doxygen group definitions
00050    ------------------------------------------------------ */
00058 #ifndef IXATMTYPES_H
00059 #define IXATMTYPES_H
00060 
00061 #include "IxNpeA.h"
00062 
00072 typedef enum
00073 {
00074     IX_UTOPIA_PORT_0 = 0,  
00075 #ifdef IX_NPE_MPHYMULTIPORT
00076     IX_UTOPIA_PORT_1,      
00077     IX_UTOPIA_PORT_2,      
00078     IX_UTOPIA_PORT_3,      
00079     IX_UTOPIA_PORT_4,      
00080     IX_UTOPIA_PORT_5,      
00081     IX_UTOPIA_PORT_6,      
00082     IX_UTOPIA_PORT_7,      
00083     IX_UTOPIA_PORT_8,      
00084     IX_UTOPIA_PORT_9,      
00085     IX_UTOPIA_PORT_10,     
00086     IX_UTOPIA_PORT_11,     
00087 #endif /* IX_NPE_MPHY */
00088     IX_UTOPIA_MAX_PORTS    
00091 } IxAtmLogicalPort;
00092 
00097 #define IX_ATM_CELL_PAYLOAD_SIZE             (48)
00098 
00103 #define IX_ATM_CELL_SIZE                     (53)
00104 
00109 #define IX_ATM_CELL_SIZE_NO_HEC              (IX_ATM_CELL_SIZE - 1)
00110 
00115 #define IX_ATM_OAM_CELL_SIZE_NO_HEC          IX_ATM_CELL_SIZE_NO_HEC
00116 
00121 #define IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE     IX_ATM_CELL_PAYLOAD_SIZE
00122 
00127 #define IX_ATM_AAL5_CELL_PAYLOAD_SIZE        IX_ATM_CELL_PAYLOAD_SIZE
00128 
00133 #define IX_ATM_AAL0_52_CELL_SIZE_NO_HEC      IX_ATM_CELL_SIZE_NO_HEC
00134 
00135 
00140 #define IX_ATM_MAX_VPI 255
00141 
00146 #define IX_ATM_MAX_VCI 65535
00147 
00152 #define IX_ATM_MAX_NUM_AAL_VCS 32
00153 
00161 #define IX_ATM_MAX_NUM_VC IX_ATM_MAX_NUM_AAL_VCS
00162 
00163 
00164 
00170 #define IX_ATM_MAX_NUM_OAM_TX_VCS IX_UTOPIA_MAX_PORTS
00171 
00177 #define IX_ATM_MAX_NUM_OAM_RX_VCS 1
00178 
00183 #define IX_ATM_MAX_NUM_AAL_OAM_TX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_TX_VCS)
00184 
00189 #define IX_ATM_MAX_NUM_AAL_OAM_RX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_RX_VCS)
00190 
00195 #define IX_ATM_IDLE_CELLS_CONNID 0
00196 
00197 
00202 #define IX_ATM_CELL_HEADER_VCI_GET(cellHeader) \
00203     (((cellHeader) >> 4) & IX_OAM_VCI_BITS_MASK);
00204 
00209 #define IX_ATM_CELL_HEADER_VPI_GET(cellHeader) \
00210     (((cellHeader) >> 20) & IX_OAM_VPI_BITS_MASK);
00211 
00216 #define IX_ATM_CELL_HEADER_PTI_GET(cellHeader) \
00217     ((cellHeader) >> 1) & IX_OAM_PTI_BITS_MASK;
00218 
00224 typedef unsigned int IxAtmCellHeader;
00225 
00226 
00235 typedef enum
00236 {
00237     IX_ATM_CBR,    
00238     IX_ATM_RTVBR,  
00239     IX_ATM_VBR,    
00240     IX_ATM_UBR,    
00241     IX_ATM_ABR     
00243 } IxAtmServiceCategory;
00244 
00261 typedef enum
00262 {
00263     IX_ATM_RX_A = 0,      
00264     IX_ATM_RX_B,          
00265     IX_ATM_MAX_RX_STREAMS 
00266 } IxAtmRxQueueId;
00267 
00291 typedef struct
00292 {
00293     IxAtmServiceCategory atmService; 
00294     unsigned pcr;   
00295     unsigned cdvt;  
00296     unsigned scr;   
00297     unsigned mbs;   
00298     unsigned mcr;   
00299     unsigned mfs;   
00300 } IxAtmTrafficDescriptor;
00301 
00312 typedef unsigned int IxAtmConnId;
00313 
00326 typedef int IxAtmSchedulerVcId;
00327 
00336 typedef unsigned int IxAtmNpeRxVcId;
00337 
00352 typedef struct
00353 {
00354     IxAtmConnId connId; 
00362     unsigned int numberOfCells; 
00370 } IxAtmScheduleTableEntry;
00371 
00384 typedef struct
00385 {
00386     unsigned tableSize;      
00391     unsigned totalCellSlots; 
00397     IxAtmScheduleTableEntry *table; 
00402 } IxAtmScheduleTable;
00403 
00404 #endif /* IXATMTYPES_H */
00405 
Automatically generated from sources. © Intel Corp. 2003