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IxAtmdAccCtrl.h

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00001 
00053 /* ------------------------------------------------------
00054    Doxygen group definitions
00055    ------------------------------------------------------ */
00056 
00071 #ifndef IXATMDACCCTRL_H
00072 #define IXATMDACCCTRL_H
00073 
00074 #include "IxAtmdAcc.h"
00075 
00076 /* ------------------------------------------------------
00077    AtmdAccCtrl Data Types definition
00078    ------------------------------------------------------ */
00079 
00093 #define IX_ATMDACC_PORT_DISABLE_IN_PROGRESS 5
00094 
00110 #define IX_ATMDACC_ALLPDUS 0xffffffff
00111 
00112 /* ------------------------------------------------------
00113    Part of the IxAtmdAcc interface related to RX traffic
00114    ------------------------------------------------------ */
00115 
00144 typedef IX_STATUS (*IxAtmdAccRxDispatcher) (IxAtmRxQueueId rxQueueId,
00145                          unsigned int numberOfPdusToProcess,
00146                          unsigned int *reservedPtr);
00147 
00148 /* ------------------------------------------------------
00149    Part of the IxAtmdAcc interface related to TX traffic
00150    ------------------------------------------------------ */
00151 
00195 typedef IX_STATUS (*IxAtmdAccTxDoneDispatcher) (unsigned int numberOfPdusToProcess,
00196                                                 unsigned int *reservedPtr);
00197 
00224 typedef void (*IxAtmdAccPortTxLowCallback) (IxAtmLogicalPort port,
00225                            unsigned int numberOfAvailableCells);
00226 
00255 typedef IX_STATUS (*IxAtmdAccTxVcDemandUpdateCallback) (IxAtmLogicalPort port,
00256                         int vcId,
00257                         unsigned int numberOfCells);
00258 
00289 typedef void (*IxAtmdAccTxVcDemandClearCallback) (IxAtmLogicalPort port,
00290                              int vcId);
00291 
00324 typedef IX_STATUS (*IxAtmdAccTxSchVcIdGetCallback) (IxAtmLogicalPort port,
00325                                unsigned int vpi,
00326                                unsigned int vci,
00327                                IxAtmConnId connId,
00328                                int *vcId);
00329 
00330 /* ------------------------------------------------------
00331    Part of the IxAtmdAcc interface related to RX traffic
00332    ------------------------------------------------------ */
00333 
00371 PUBLIC IX_STATUS ixAtmdAccRxDispatcherRegister (
00372                           IxAtmRxQueueId queueId,
00373                           IxAtmdAccRxDispatcher callback);
00374 
00435 PUBLIC IX_STATUS ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId,
00436     unsigned int numberOfPdusToProcess,
00437     unsigned int *numberOfPdusProcessedPtr);
00438 
00464 PUBLIC IX_STATUS ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId,
00465                      unsigned int *numberOfPdusPtr);
00466 
00493 PUBLIC IX_STATUS ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId,
00494                      unsigned int *numberOfPdusPtr);
00495 
00496 /* ------------------------------------------------------
00497    Part of the IxAtmdAcc interface related to TX traffic
00498    ------------------------------------------------------ */
00499 
00533 PUBLIC IX_STATUS ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port,
00534                          unsigned int *numberOfCellsPtr);
00535 
00576 PUBLIC IX_STATUS ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port,
00577                        unsigned int numberOfCells,
00578                        IxAtmdAccPortTxLowCallback callback);
00579 
00642 PUBLIC IX_STATUS ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port,
00643     IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback,
00644     IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback,
00645     IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback);
00646 
00726 PUBLIC IX_STATUS ixAtmdAccPortTxProcess (IxAtmLogicalPort port,
00727     IxAtmScheduleTable* scheduleTablePtr);
00728 
00777 PUBLIC IX_STATUS
00778 ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess,
00779                 unsigned int *numberOfPdusProcessedPtr);
00780 
00811 PUBLIC IX_STATUS
00812 ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr);
00813 
00843 PUBLIC IX_STATUS
00844 ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr);
00845 
00902 PUBLIC IX_STATUS ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus,
00903    IxAtmdAccTxDoneDispatcher notificationCallback);
00904 
00905 /* ------------------------------------------------------
00906    Part of the IxAtmdAcc interface related to Utopia config
00907    ------------------------------------------------------ */
00908 
00937 typedef struct
00938 {
00944     struct UtTxConfig_
00945     {
00946 
00947     unsigned int reserved_1:1;  
00948     unsigned int txInterface:1;     
00954     unsigned int txMode:1;      
00959     unsigned int txOctet:1;  
00965     unsigned int txParity:1;    
00970     unsigned int txEvenParity:1; 
00974     unsigned int txHEC:1; 
00979     unsigned int txCOSET:1;    
00985     unsigned int reserved_2:1;    
00987     unsigned int txCellSize:7;    
00990     unsigned int reserved_3:3;  
00991     unsigned int txAddrRange:5;       
00995     unsigned int reserved_4:3;      
00996     unsigned int txPHYAddr:5;     
00999     }
01000 
01001     utTxConfig;       
01008     struct UtTxStatsConfig_
01009     {
01010 
01011     unsigned int vpi:12;  
01014     unsigned int vci:16;  
01016     unsigned int pti:3;  
01021     unsigned int clp:1;  
01025     }
01026 
01027     utTxStatsConfig;       
01034     struct UtTxDefineIdle_
01035     {
01036 
01037     unsigned int vpi:12;  
01040     unsigned int vci:16;  
01042     unsigned int pti:3;  
01045     unsigned int clp:1;  
01047     }
01048 
01049     utTxDefineIdle;      
01056     struct UtTxEnableFields_
01057     {
01058 
01059     unsigned int defineTxIdleGFC:1;    
01064     unsigned int defineTxIdlePTI:1;    
01069     unsigned int defineTxIdleCLP:1;    
01074     unsigned int phyStatsTxEnb:1;    
01080     unsigned int vcStatsTxEnb:1;  
01086     unsigned int vcStatsTxGFC:1;  
01093     unsigned int vcStatsTxPTI:1;  
01098     unsigned int vcStatsTxCLP:1;  
01103     unsigned int reserved_1:3;  
01105     unsigned int txPollStsInt:1;    
01110     unsigned int txCellOvrInt:1;    
01115     unsigned int txIdleCellOvrInt:1;  
01119     unsigned int enbIdleCellCnt:1;    
01123     unsigned int enbTxCellCnt:1;    
01127     unsigned int reserved_2:16;   
01128     } utTxEnableFields;  
01135     struct UtTxTransTable0_
01136     {
01137 
01138     unsigned int phy0:5;  
01140     unsigned int phy1:5;  
01142     unsigned int phy2:5;  
01144     unsigned int reserved_1:1;  
01146     unsigned int phy3:5;  
01148     unsigned int phy4:5;  
01150     unsigned int phy5:5;  
01152     unsigned int reserved_2:1;  
01153     } utTxTransTable0;  
01160     struct UtTxTransTable1_
01161     {
01162 
01163     unsigned int phy6:5;  
01165     unsigned int phy7:5;  
01167     unsigned int phy8:5;  
01169     unsigned int reserved_1:1; 
01171     unsigned int phy9:5;  
01173     unsigned int phy10:5;   
01175     unsigned int phy11:5;   
01177     unsigned int reserved_2:1;  
01178     } utTxTransTable1;  
01185     struct UtTxTransTable2_
01186     {
01187 
01188     unsigned int phy12:5;   
01190     unsigned int phy13:5;   
01192     unsigned int phy14:5;   
01194     unsigned int reserved_1:1; 
01196     unsigned int phy15:5;   
01198     unsigned int phy16:5;   
01200     unsigned int phy17:5;   
01202     unsigned int reserved_2:1;  
01203     } utTxTransTable2;    
01210     struct UtTxTransTable3_
01211     {
01212 
01213     unsigned int phy18:5;   
01215     unsigned int phy19:5;   
01217     unsigned int phy20:5;   
01219     unsigned int reserved_1:1; 
01221     unsigned int phy21:5;   
01223     unsigned int phy22:5;   
01225     unsigned int phy23:5;   
01227     unsigned int reserved_2:1;  
01228     } utTxTransTable3;  
01235     struct UtTxTransTable4_
01236     {
01237 
01238     unsigned int phy24:5;   
01240     unsigned int phy25:5;   
01242     unsigned int phy26:5;   
01244     unsigned int reserved_1:1; 
01246     unsigned int phy27:5;   
01248     unsigned int phy28:5;   
01250     unsigned int phy29:5;   
01252     unsigned int reserved_2:1;  
01253     } utTxTransTable4;  
01260     struct UtTxTransTable5_
01261     {
01262 
01263     unsigned int phy30:5;   
01265     unsigned int reserved_1:27;     
01267     } utTxTransTable5;  
01274     struct UtRxConfig_
01275     {
01276 
01277     unsigned int rxInterface:1;    
01282     unsigned int rxMode:1;      
01287     unsigned int rxOctet:1;  
01293     unsigned int rxParity:1;    
01297     unsigned int rxEvenParity:1;
01301     unsigned int rxHEC:1;    
01306     unsigned int rxCOSET:1;  
01311     unsigned int rxHECpass:1;    
01317     unsigned int reserved_1:1;    
01319     unsigned int rxCellSize:7;    
01322     unsigned int rxHashEnbGFC:1;      
01328     unsigned int rxPreHash:1; 
01334     unsigned int reserved_2:1;    
01336     unsigned int rxAddrRange:5;     
01341     unsigned int reserved_3:3;    
01342     unsigned int rxPHYAddr:5;     
01345     } utRxConfig;  
01352     struct UtRxStatsConfig_
01353     {
01354 
01355     unsigned int vpi:12;  
01358     unsigned int vci:16;  
01360     unsigned int pti:3;  
01365     unsigned int clp:1;  
01369     } utRxStatsConfig;  
01376     struct UtRxDefineIdle_
01377     {
01378 
01379     unsigned int vpi:12;  
01382     unsigned int vci:16;  
01384     unsigned int pti:3;  
01387     unsigned int clp:1;  
01389     } utRxDefineIdle;      
01396     struct UtRxEnableFields_
01397     {
01398 
01399     unsigned int defineRxIdleGFC:1;
01404     unsigned int defineRxIdlePTI:1;
01409     unsigned int defineRxIdleCLP:1;
01414     unsigned int phyStatsRxEnb:1;
01420     unsigned int vcStatsRxEnb:1;
01425     unsigned int vcStatsRxGFC:1;
01431     unsigned int vcStatsRxPTI:1;
01436     unsigned int vcStatsRxCLP:1;
01441     unsigned int discardHecErr:1;
01445     unsigned int discardParErr:1;
01449     unsigned int discardIdle:1;    
01453     unsigned int enbHecErrCnt:1;
01457     unsigned int enbParErrCnt:1;
01461     unsigned int enbIdleCellCnt:1;
01465     unsigned int enbSizeErrCnt:1;
01469     unsigned int enbRxCellCnt:1;
01473     unsigned int reserved_1:3;    
01475     unsigned int rxCellOvrInt:1;      
01480     unsigned int invalidHecOvrInt:1;  
01485     unsigned int invalidParOvrInt:1;  
01490     unsigned int invalidSizeOvrInt:1;   
01495     unsigned int rxIdleOvrInt:1;      
01499     unsigned int reserved_2:3;    
01501     unsigned int rxAddrMask:5;    
01505     } utRxEnableFields;      
01512     struct UtRxTransTable0_
01513     {
01514 
01515     unsigned int phy0:5;  
01517     unsigned int phy1:5;  
01519     unsigned int phy2:5;  
01521     unsigned int reserved_1:1;  
01523     unsigned int phy3:5;  
01525     unsigned int phy4:5;  
01527     unsigned int phy5:5;  
01529     unsigned int reserved_2:1;  
01530     }
01531 
01532     utRxTransTable0;  
01539     struct UtRxTransTable1_
01540     {
01541 
01542     unsigned int phy6:5;  
01544     unsigned int phy7:5;  
01546     unsigned int phy8:5;  
01548     unsigned int reserved_1:1; 
01550     unsigned int phy9:5;  
01552     unsigned int phy10:5;   
01554     unsigned int phy11:5;   
01556     unsigned int reserved_2:1;  
01557     }
01558 
01559     utRxTransTable1;  
01566     struct UtRxTransTable2_
01567     {
01568 
01569     unsigned int phy12:5;   
01571     unsigned int phy13:5;   
01573     unsigned int phy14:5;   
01575     unsigned int reserved_1:1; 
01577     unsigned int phy15:5;   
01579     unsigned int phy16:5;   
01581     unsigned int phy17:5;   
01583     unsigned int reserved_2:1;  
01584     } utRxTransTable2;    
01591     struct UtRxTransTable3_
01592     {
01593 
01594     unsigned int phy18:5;   
01596     unsigned int phy19:5;   
01598     unsigned int phy20:5;   
01600     unsigned int reserved_1:1; 
01602     unsigned int phy21:5;   
01604     unsigned int phy22:5;   
01606     unsigned int phy23:5;   
01608     unsigned int reserved_2:1;  
01609     } utRxTransTable3;  
01616     struct UtRxTransTable4_
01617     {
01618 
01619     unsigned int phy24:5;   
01621     unsigned int phy25:5;   
01623     unsigned int phy26:5;   
01625     unsigned int reserved_1:1; 
01627     unsigned int phy27:5;   
01629     unsigned int phy28:5;   
01631     unsigned int phy29:5;   
01633     unsigned int reserved_2:1;  
01634     } utRxTransTable4;  
01641     struct UtRxTransTable5_
01642     {
01643 
01644     unsigned int phy30:5;   
01646     unsigned int reserved_1:27;     
01648     } utRxTransTable5;  
01655     struct UtSysConfig_
01656     {
01657 
01658     unsigned int reserved_1:2;     
01659     unsigned int txEnbFSM:1;    
01663     unsigned int rxEnbFSM:1;    
01667     unsigned int disablePins:1;    
01673     unsigned int tstLoop:1;    
01680     unsigned int txReset:1;   
01687     unsigned int rxReset:1;   
01694     unsigned int reserved_2:24;     
01695     } utSysConfig;  
01697 }
01698 IxAtmdAccUtopiaConfig;
01699 
01711 typedef struct
01712 {
01713 
01714     unsigned int utTxCellCount;  
01716     unsigned int utTxIdleCellCount;    
01723     struct UtTxCellConditionStatus_
01724     {
01725 
01726     unsigned int reserved_1:2;   
01727     unsigned int txFIFO2Underflow:1; 
01731     unsigned int txFIFO1Underflow:1; 
01735     unsigned int txFIFO2Overflow:1;  
01739     unsigned int txFIFO1Overflow:1; 
01743     unsigned int txIdleCellCountOvr:1; 
01746     unsigned int txCellCountOvr:1; 
01749     unsigned int reserved_2:24;    
01750     } utTxCellConditionStatus;    
01752     unsigned int utRxCellCount; 
01753     unsigned int utRxIdleCellCount;    
01754     unsigned int utRxInvalidHECount;     
01757     unsigned int utRxInvalidParCount;  
01760     unsigned int utRxInvalidSizeCount;  
01770     struct UtRxCellConditionStatus_
01771     {
01772 
01773     unsigned int reserved_1:3;  
01774     unsigned int rxCellCountOvr:1;      
01775     unsigned int invalidHecCountOvr:1;    
01776     unsigned int invalidParCountOvr:1;    
01777     unsigned int invalidSizeCountOvr:1;    
01778     unsigned int rxIdleCountOvr:1;      
01779     unsigned int reserved_2:4;  
01780     unsigned int rxFIFO2Underflow:1;  
01783     unsigned int rxFIFO1Underflow:1;  
01786     unsigned int rxFIFO2Overflow:1;    
01789     unsigned int rxFIFO1Overflow:1;    
01792     unsigned int reserved_3:16;      
01793     } utRxCellConditionStatus;    
01795 } IxAtmdAccUtopiaStatus;
01796 
01830 PUBLIC IX_STATUS ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig *
01831                         ixAtmdAccUtopiaConfigPtr);
01832 
01858 PUBLIC IX_STATUS ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus *
01859                         ixAtmdAccUtopiaStatus);
01860 
01893 PUBLIC IX_STATUS ixAtmdAccPortEnable (IxAtmLogicalPort port);
01894 
01926 PUBLIC IX_STATUS ixAtmdAccPortDisable (IxAtmLogicalPort port);
01927 
01951 PUBLIC BOOL ixAtmdAccPortDisableComplete (IxAtmLogicalPort port);
01952 
01953 #endif /* IXATMDACCCTRL_H */
01954 
Automatically generated from sources. © Intel Corp. 2003