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IxNpeA.h File Reference

Header file for the IXP425 ATM NPE API. More...

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Data Structures

struct  IxNpeA_NpePacketDescriptor
 HSS Packetized NpePacket Descriptor Structure. More...

struct  IxNpeA_RxAtmVc
 Rx Descriptor definition. More...

struct  IxNpeA_TxAtmVc
 Tx Descriptor definition. More...


Defines

#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE
 ATM Message ID command to write the data to the offset in the Utopia Configuration Table.

#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD
 ATM Message ID command triggers the NPE to copy the Utopia Configuration Table to the Utopia coprocessor.

#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD
 ATM Message ID command triggers the NPE to read-back the Utopia status registers and update the Utopia Status Table.

#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ
 ATM Message ID command to read the Utopia Status Table at the specified offset.

#define IX_NPE_A_MSSG_ATM_TX_ENABLE
 ATM Message ID command triggers the NPE to re-enable processing of any entries on the TxVcQ for this port.

#define IX_NPE_A_MSSG_ATM_TX_DISABLE
 ATM Message ID command triggers the NPE to disable processing on this port.

#define IX_NPE_A_MSSG_ATM_RX_ENABLE
 ATM Message ID command triggers the NPE to process any received cells for this VC according to the VC Lookup Table.

#define IX_NPE_A_MSSG_ATM_RX_DISABLE
 ATM Message ID command triggers the NPE to disable processing for this VC.

#define IX_NPE_A_MSSG_ATM_STATUS_READ
 ATM Message ID command to read the ATM status. The data is returned via a response message.

#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE
 HSS Message ID command writes the ConfigWord value to the location in the HSS_CONFIG_TABLE specified by offset for HSS port hPort.

#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD
 HSS Message ID command triggers the NPE to copy the contents of the HSS Configuration Table to the appropriate configuration registers in the HSS coprocessor for the port specified by hPort.

#define IX_NPE_A_MSSG_HSS_PORT_ERROR_READ
 HSS Message ID command triggers the NPE to return an HssErrorReadResponse message for HSS port hPort.

#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE
 HSS Message ID command triggers the NPE to reset internal status and enable the HssChannelized operation on the HSS port specified by hPort.

#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE
 HSS Message ID command triggers the NPE to disable the HssChannelized operation on the HSS port specified by hPort.

#define IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE
 HSS Message ID command writes the HSSnC_IDLE_PATTERN value for HSS port hPort. (n=hPort).

#define IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE
 HSS Message ID command writes the HSSnC_NUM_CHANNELS value for HSS port hPort. (n=hPort).

#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE
 HSS Message ID command writes the HSSnC_RX_BUF_ADDR value for HSS port hPort. (n=hPort).

#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE
 HSS Message ID command writes the HSSnC_RX_BUF_SIZEB and HSSnC_RX_TRIG_PERIOD values for HSS port hPort. (n=hPort).

#define IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE
 HSS Message ID command writes the HSSnC_TX_BLK1_SIZEB, HSSnC_TX_BLK1_SIZEW, HSSnC_TX_BLK2_SIZEB, and HSSnC_TX_BLK2_SIZEW values for HSS port hPort. (n=hPort).

#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE
 HSS Message ID command writes the HSSnC_TX_BUF_ADDR value for HSS port hPort. (n=hPort).

#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE
 HSS Message ID command writes the HSSnC_TX_BUF_SIZEN value for HSS port hPort. (n=hPort).

#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE
 HSS Message ID command triggers the NPE to reset internal status and enable the HssPacketized operation for the flow specified by pPipe on the HSS port specified by hPort.

#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE
 HSS Message ID command triggers the NPE to disable the HssPacketized operation for the flow specified by pPipe on the HSS port specified by hPort.

#define IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE
 HSS Message ID command writes the HSSnP_NUM_PIPES value for HSS port hPort.(n=hPort).

#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE
 HSS Message ID command writes the HSSnP_PIPEp_FIFOSIZEW value for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe).

#define IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE
 HSS Message ID command writes the HSSnP_PIPEp_HDLC_RXCFG and HSSnP_PIPEp_HDLC_TXCFG values for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe).

#define IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE
 HSS Message ID command writes the HSSnP_PIPEp_IDLE_PATTERN value for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe).

#define IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE
 HSS Message ID command writes the HSSnP_PIPEp_RXSIZEB value for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe).

#define IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE
 HSS Message ID command writes the HSSnP_PIPEp_MODE value for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe).

#define IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET
 ATM Descriptor structure offset for Receive Descriptor Status field.

#define IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET
 ATM Descriptor structure offset for Receive Descriptor VC ID field.

#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET
 ATM Descriptor structure offset for Receive Descriptor Current Mbuf Size field.

#define IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET
 ATM Descriptor structure offset for Receive Descriptor ATM Header.

#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET
 ATM Descriptor structure offset for Receive Descriptor Current MBuf length.

#define IX_NPE_A_RXDESCRIPTOR_TIMELIMIT_OFFSET
#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET
 ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer.

#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET
 ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer.

#define IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET
 ATM Descriptor structure offset for Receive Descriptor Next MBuf Pointer.

#define IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET
 ATM Descriptor structure offset for Receive Descriptor Total Length.

#define IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
 ATM Descriptor structure offset for Receive Descriptor AAL5 CRC Residue.

#define IX_NPE_A_RXDESCRIPTOR_SIZE
 ATM Descriptor structure offset for Receive Descriptor Size.

#define IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET
 ATM Descriptor structure offset for Transmit Descriptor Port.

#define IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET
 ATM Descriptor structure offset for Transmit Descriptor RSVD.

#define IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET
 ATM Descriptor structure offset for Transmit Descriptor Current MBuf Length.

#define IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET
 ATM Descriptor structure offset for Transmit Descriptor ATM Header.

#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET
 ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf chain.

#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET
 ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf Data.

#define IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET
 ATM Descriptor structure offset for Transmit Descriptor Pointer to the Next MBuf chain.

#define IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET
 ATM Descriptor structure offset for Transmit Descriptor Total Length.

#define IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
 ATM Descriptor structure offset for Transmit Descriptor AAL5 CRC Residue.

#define IX_NPE_A_TXDESCRIPTOR_SIZE
 ATM Descriptor structure offset for Transmit Descriptor Size.

#define IX_NPE_MPHYMULTIPORT
 Define this macro to enable MPHY mode.

#define IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK
 The NPE reserves the High Watermark for its operation. But it must be set by the Xscale.

#define IX_NPE_A_QMQ_ATM_TX_DONE
 Queue ID for ATM Transmit Done queue.

#define IX_NPE_A_QMQ_ATM_TX0
 Queue ID for ATM transmit Queue in a single phy configuration.

#define IX_NPE_A_QMQ_ATM_TX1
 Queue ID for ATM transmit Queue Multiphy from 1 to 11.

#define IX_NPE_A_QMQ_ATM_TX2
#define IX_NPE_A_QMQ_ATM_TX3
#define IX_NPE_A_QMQ_ATM_TX4
#define IX_NPE_A_QMQ_ATM_TX5
#define IX_NPE_A_QMQ_ATM_TX6
#define IX_NPE_A_QMQ_ATM_TX7
#define IX_NPE_A_QMQ_ATM_TX8
#define IX_NPE_A_QMQ_ATM_TX9
#define IX_NPE_A_QMQ_ATM_TX10
#define IX_NPE_A_QMQ_ATM_TX11
#define IX_NPE_A_QMQ_ATM_TXID_MIN
 Queue Manager Queue ID for ATM transmit Queue with minimum number of queue.

#define IX_NPE_A_QMQ_ATM_TXID_MAX
 Queue Manager Queue ID for ATM transmit Queue with maximum number of queue.

#define IX_NPE_A_QMQ_ATM_RX_HI
 Queue Manager Queue ID for ATM Receive high Queue.

#define IX_NPE_A_QMQ_ATM_RX_LO
 Queue Manager Queue ID for ATM Receive low Queue.

#define IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG
 Hardware QMgr Queue ID for HSS Port 0 Channelized Receive trigger.

#define IX_NPE_A_QMQ_HSS0_PKT_RX
 Hardware QMgr Queue ID for HSS Port 0 Packetized Receive.

#define IX_NPE_A_QMQ_HSS0_PKT_TX0
 Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 0.

#define IX_NPE_A_QMQ_HSS0_PKT_TX1
 Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 1.

#define IX_NPE_A_QMQ_HSS0_PKT_TX2
 Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 2.

#define IX_NPE_A_QMQ_HSS0_PKT_TX3
 Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 3.

#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0
 Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 0.

#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1
 Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 1.

#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2
 Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 2.

#define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3
 Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 3.

#define IX_NPE_A_QMQ_HSS0_PKT_TX_DONE
 Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit Done queue.

#define IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG
 Hardware QMgr Queue ID for HSS Port 1 Channelized Receive trigger.

#define IX_NPE_A_QMQ_HSS1_PKT_RX
 Hardware QMgr Queue ID for HSS Port 1 Packetized Receive.

#define IX_NPE_A_QMQ_HSS1_PKT_TX0
 Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 0.

#define IX_NPE_A_QMQ_HSS1_PKT_TX1
 Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 1.

#define IX_NPE_A_QMQ_HSS1_PKT_TX2
 Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 2.

#define IX_NPE_A_QMQ_HSS1_PKT_TX3
 Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 3.

#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0
 Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 0.

#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1
 Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 1.

#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2
 Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 2.

#define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3
 Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 3.

#define IX_NPE_A_QMQ_HSS1_PKT_TX_DONE
 Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit Done queue.

#define IX_NPE_A_QMQ_ATM_FREE_VC0
 Hardware QMgr Queue ID for ATM Free VC Queue.

#define IX_NPE_A_QMQ_ATM_FREE_VC1
#define IX_NPE_A_QMQ_ATM_FREE_VC2
#define IX_NPE_A_QMQ_ATM_FREE_VC3
#define IX_NPE_A_QMQ_ATM_FREE_VC4
#define IX_NPE_A_QMQ_ATM_FREE_VC5
#define IX_NPE_A_QMQ_ATM_FREE_VC6
#define IX_NPE_A_QMQ_ATM_FREE_VC7
#define IX_NPE_A_QMQ_ATM_FREE_VC8
#define IX_NPE_A_QMQ_ATM_FREE_VC9
#define IX_NPE_A_QMQ_ATM_FREE_VC10
#define IX_NPE_A_QMQ_ATM_FREE_VC11
#define IX_NPE_A_QMQ_ATM_FREE_VC12
#define IX_NPE_A_QMQ_ATM_FREE_VC13
#define IX_NPE_A_QMQ_ATM_FREE_VC14
#define IX_NPE_A_QMQ_ATM_FREE_VC15
#define IX_NPE_A_QMQ_ATM_FREE_VC16
#define IX_NPE_A_QMQ_ATM_FREE_VC17
#define IX_NPE_A_QMQ_ATM_FREE_VC18
#define IX_NPE_A_QMQ_ATM_FREE_VC19
#define IX_NPE_A_QMQ_ATM_FREE_VC20
#define IX_NPE_A_QMQ_ATM_FREE_VC21
#define IX_NPE_A_QMQ_ATM_FREE_VC22
#define IX_NPE_A_QMQ_ATM_FREE_VC23
#define IX_NPE_A_QMQ_ATM_FREE_VC24
#define IX_NPE_A_QMQ_ATM_FREE_VC25
#define IX_NPE_A_QMQ_ATM_FREE_VC26
#define IX_NPE_A_QMQ_ATM_FREE_VC27
#define IX_NPE_A_QMQ_ATM_FREE_VC28
#define IX_NPE_A_QMQ_ATM_FREE_VC29
#define IX_NPE_A_QMQ_ATM_FREE_VC30
#define IX_NPE_A_QMQ_ATM_FREE_VC31
#define IX_NPE_A_QMQ_ATM_RXFREE_MIN
 The minimum queue ID for FreeVC queue.

#define IX_NPE_A_QMQ_ATM_RXFREE_MAX
 The maximum queue ID for FreeVC queue.

#define IX_NPE_A_QMQ_OAM_FREE_VC
 OAM Rx Free queue ID.

#define IX_NPE_A_CHAIN_DESC_COUNT_MAX
 Maximum number of chained MBufs that can be chained together.

#define GFC_MASK
 Mask to acess GFC.

#define IX_NPE_A_ATMCELLHEADER_GFC_GET(header)
 return GFC from ATM cell header

#define IX_NPE_A_ATMCELLHEADER_GFC_SET(header, gfc)
 set GFC into ATM cell header

#define VPI_MASK
 Mask to acess VPI.

#define IX_NPE_A_ATMCELLHEADER_VPI_GET(header)
 return VPI from ATM cell header

#define IX_NPE_A_ATMCELLHEADER_VPI_SET(header, vpi)
 set VPI into ATM cell header

#define VCI_MASK
 Mask to acess VCI.

#define IX_NPE_A_ATMCELLHEADER_VCI_GET(header)
 return VCI from ATM cell header

#define IX_NPE_A_ATMCELLHEADER_VCI_SET(header, vci)
 set VCI into ATM cell header

#define PTI_MASK
 Mask to acess PTI.

#define IX_NPE_A_ATMCELLHEADER_PTI_GET(header)
 return PTI from ATM cell header

#define IX_NPE_A_ATMCELLHEADER_PTI_SET(header, pti)
 set PTI into ATM cell header

#define CLP_MASK
 Mask to acess CLP.

#define IX_NPE_A_ATMCELLHEADER_CLP_GET(header)
 return CLP from ATM cell header

#define IX_NPE_A_ATMCELLHEADER_CLP_SET(header, clp)
 set CLP into ATM cell header

#define STATUS_MASK
 Mask to acess the rxBitField status.

#define IX_NPE_A_RXBITFIELD_STATUS_GET(rxbitfield)
 return the rxBitField status

#define IX_NPE_A_RXBITFIELD_STATUS_SET(rxbitfield, status)
 set the rxBitField status

#define PORT_MASK
 Mask to acess the rxBitField port.

#define IX_NPE_A_RXBITFIELD_PORT_GET(rxbitfield)
 return the rxBitField port

#define IX_NPE_A_RXBITFIELD_PORT_SET(rxbitfield, port)
 set the rxBitField port

#define VCID_MASK
 Mask to acess the rxBitField vcId.

#define IX_NPE_A_RXBITFIELD_VCID_GET(rxbitfield)
 return the rxBitField vcId

#define IX_NPE_A_RXBITFIELD_VCID_SET(rxbitfield, vcid)
 set the rxBitField vcId

#define CURRMBUFSIZE_MASK
 Mask to acess the rxBitField mbuf size.

#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET(rxbitfield)
 return the rxBitField mbuf size

#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET(rxbitfield, currmbufsize)
 set the rxBitField mbuf size


Enumerations

enum  IxNpeA_AalType {
  IX_NPE_A_AAL_TYPE_INVALID,
  IX_NPE_A_AAL_TYPE_0_48,
  IX_NPE_A_AAL_TYPE_0_52,
  IX_NPE_A_AAL_TYPE_5,
  IX_NPE_A_AAL_TYPE_OAM
}
 NPE-A AAL Type. More...

enum  IxNpeA_PayloadFormat {
  IX_NPE_A_52_BYTE_PAYLOAD,
  IX_NPE_A_48_BYTE_PAYLOAD
}
 NPE-A Payload format 52-bytes & 48-bytes. More...


Detailed Description

Header file for the IXP425 ATM NPE API.

Date:
22-Mar-2002

Version:
Revision
1.50
-- Intel Copyright Notice --
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For further details, please see the file README.TXT distributed with this software.
-- End Intel Copyright Notice --

Definition in file IxNpeA.h.

Automatically generated from sources. © Intel Corp. 2003