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usbprivateconstants.h00001 00042 /* 00043 * Private constants used by the USB Driver's support API 00044 * 00045 */ 00046 00047 #ifndef usbprivateconstants_H 00048 #define usbprivateconstants_H 00049 00050 typedef enum /* USBToken */ 00051 { 00052 UNKNOWN_TOKEN = 0, 00053 SETUP_TOKEN, 00054 IN_TOKEN, 00055 OUT_TOKEN 00056 } USBToken; 00057 00058 typedef enum /* EP0State */ 00059 { 00060 IDLE = 0, 00061 ACTIVE_IN, 00062 ACTIVE_OUT, 00063 END_IN_XFER, 00064 END_OUT_XFER 00065 } EP0State; 00066 00067 typedef enum /* USBControlTransfer */ 00068 { 00069 UNKNOWN_TRANSFER = 0, 00070 CONTROL_READ, 00071 CONTROL_WRITE, 00072 CONTROL_NO_DATA 00073 } USBControlTransfer; 00074 00075 /* Masks for UDC Registers */ 00076 00077 /* USB Control Register (UDCCR) */ 00078 #define UDC_UDCCR_UDE ( 0x1 << 0 ) /* UDC enabled */ 00079 #define UDC_UDCCR_UDA ( 0x1 << 1 ) /* READ-ONLY: udc is active */ 00080 #define UDC_UDCCR_RSM ( 0x1 << 2 ) /* Forces the usb out of suspend state */ 00081 #define UDC_UDCCR_RESIR ( 0x1 << 3 ) /* UDC received resume signalling from host */ 00082 #define UDC_UDCCR_SUSIR ( 0x1 << 4 ) /* UDC receive suspend signalling from host */ 00083 #define UDC_UDCCR_SRM ( 0x1 << 5 ) /* Suspend/Resume interrupt disabled */ 00084 #define UDC_UDCCR_RSTIR ( 0x1 << 6 ) /* Set when the host issues a UDC reset */ 00085 #define UDC_UDCCR_REM ( 0x1 << 7 ) /* Reset interrupt disabled */ 00086 00087 /* UDC Endpoint 0 Control/Status Register (UDCCS0) */ 00088 #define UDC_UDCCS0_OPR ( 0x1 << 0 ) /* OUT packet to endpoint zero received */ 00089 #define UDC_UDCCS0_IPR ( 0x1 << 1 ) /* Packet has been written to endpoint zero FIFO */ 00090 #define UDC_UDCCS0_FTF ( 0x1 << 2 ) /* Flush the Tx FIFO */ 00091 #define UDC_UDCCS0_DRWF ( 0x1 << 3 ) 00092 #define UDC_UDCCS0_SST ( 0x1 << 4 ) /* UDC sent stall handshake */ 00093 #define UDC_UDCCS0_FST ( 0x1 << 5 ) /* Force the UDC to issue a stall handshake */ 00094 #define UDC_UDCCS0_RNE ( 0x1 << 6 ) /* There is unread data in the Rx FIFO */ 00095 #define UDC_UDCCS0_SA ( 0x1 << 7 ) /* Current packet in FIFO is part of UDC setup command */ 00096 00097 /* UDC IN Endpoint Control/Status Register (UDCCS_IN) */ 00098 #define UDC_UDCCS_TFS_IN ( 0x1 << 0 ) /* Tx FIFO has room for at least one packet */ 00099 #define UDC_UDCCS_TPC_IN ( 0x1 << 1 ) /* Packet sent and err/status bits valid */ 00100 #define UDC_UDCCS_TUR_IN ( 0x1 << 3 ) /* Tx FIFO experienced underrun */ 00101 #define UDC_UDCCS_SST_IN ( 0x1 << 4 ) /* Write 1 to clear. Stall was sent */ 00102 #define UDC_UDCCS_FST_IN ( 0x1 << 5 ) /* Issue stall handshake */ 00103 #define UDC_UDCCS_TSP_IN ( 0X1 << 7 ) /* Short packet ready for transmission */ 00104 00105 /* UDC OUT Endpoint Control/Status Register (UDCCS_OUT) */ 00106 #define UDC_UDCCS_RFS_OUT ( 0x1 << 0 ) /* Rx FIFO has 1 or more packets */ 00107 #define UDC_UDCCS_RPC_OUT ( 0x1 << 1 ) /* Rx packet received and err/stats valid */ 00108 #define UDC_UDCCS_DME_OUT ( 0x1 << 3 ) /* DMA Enable */ 00109 #define UDC_UDCCS_SST_OUT ( 0x1 << 4 ) /* Stall handshake was sent */ 00110 #define UDC_UDCCS_FST_OUT ( 0x1 << 5 ) /* Issue stall handshake to OUT tokens */ 00111 #define UDC_UDCCS_RNE_OUT ( 0x1 << 6 ) /* Receive FIFO is not empty */ 00112 #define UDC_UDCCS_RSP_OUT ( 0x1 << 7 ) /* Short packet ready for reading */ 00113 00114 /* Used both for IN and OUT endpoints to flush the FIFOs */ 00115 #define UDC_UDCCS_FTF ( 0x1 << 2 ) /* Flush Rx/Tx FIFO */ 00116 00117 /* UDC Control Endpoint special bits for Isochronous endpoints */ 00118 #define UDC_UDCCS_ROF_OUT ( 0x1 << 2 ) /* Receive overflow */ 00119 00120 /* UDC Interrupt Control Register 0 (UICR0) */ 00121 #define UDC_UICR0_IM0 ( 0x1 << 0 ) /* Endpoint 0 interrupt disabled */ 00122 #define UDC_UICR0_IM1 ( 0x1 << 1 ) /* Endpoint 1 Tx interrupt disabled */ 00123 #define UDC_UICR0_IM2 ( 0x1 << 2 ) /* Endpoint 2 Rx interrupt disabled */ 00124 #define UDC_UICR0_IM3 ( 0x1 << 3 ) /* Endpoint 3 Tx interrupt disabled */ 00125 #define UDC_UICR0_IM4 ( 0x1 << 4 ) /* Endpoint 4 Rx interrupt disabled */ 00126 #define UDC_UICR0_IM5 ( 0x1 << 5 ) /* Endpoint 5 Tx interrupt disabled */ 00127 #define UDC_UICR0_IM6 ( 0x1 << 6 ) /* Endpoint 6 Tx interrupt disabled */ 00128 #define UDC_UICR0_IM7 ( 0x1 << 7 ) /* Endpoint 7 Rx interrupt disabled */ 00129 00130 /* UDC Interrupt Control Register 1 (UICR1) */ 00131 #define UDC_UICR1_IM8 ( 0x1 << 0 ) /* Endpoint 8 Tx interrupt disabled */ 00132 #define UDC_UICR1_IM9 ( 0x1 << 1 ) /* Endpoint 9 Rx interrupt disabled */ 00133 #define UDC_UICR1_IM10 ( 0x1 << 2 ) /* Endpoint 10 Rx interrupt disabled */ 00134 #define UDC_UICR1_IM11 ( 0x1 << 3 ) /* Endpoint 11 Tx interrupt disabled */ 00135 #define UDC_UICR1_IM12 ( 0x1 << 4 ) /* Endpoint 12 Rx interrupt disabled */ 00136 #define UDC_UICR1_IM13 ( 0x1 << 5 ) /* Endpoint 13 Tx interrupt disabled */ 00137 #define UDC_UICR1_IM14 ( 0x1 << 6 ) /* Endpoint 14 Rx interrupt disabled */ 00138 #define UDC_UICR1_IM15 ( 0x1 << 7 ) /* Endpoint 15 Rx interrupt disabled */ 00139 00140 /* UDC Status/Interrupt Register 0 (UISR0) */ 00141 #define UDC_UISR0_IR0 ( 0x1 << 0 ) /* Endpoint 0 needs service */ 00142 #define UDC_UISR0_IR1 ( 0x1 << 0 ) /* Endpoint 1 needs service */ 00143 #define UDC_UISR0_IR2 ( 0x1 << 0 ) /* Endpoint 2 needs service */ 00144 #define UDC_UISR0_IR3 ( 0x1 << 0 ) /* Endpoint 3 needs service */ 00145 #define UDC_UISR0_IR4 ( 0x1 << 0 ) /* Endpoint 4 needs service */ 00146 #define UDC_UISR0_IR5 ( 0x1 << 0 ) /* Endpoint 5 needs service */ 00147 #define UDC_UISR0_IR6 ( 0x1 << 0 ) /* Endpoint 6 needs service */ 00148 #define UDC_UISR0_IR7 ( 0x1 << 0 ) /* Endpoint 7 needs service */ 00149 00150 /* UDC Status/Interrupt Register 1 (UISR1) */ 00151 #define UDC_UISR1_IR8 ( 0x1 << 0 ) /* Endpoint 8 needs service */ 00152 #define UDC_UISR1_IR9 ( 0x1 << 0 ) /* Endpoint 9 needs service */ 00153 #define UDC_UISR1_IR10 ( 0x1 << 0 ) /* Endpoint 10 needs service */ 00154 #define UDC_UISR1_IR11 ( 0x1 << 0 ) /* Endpoint 11 needs service */ 00155 #define UDC_UISR1_IR12 ( 0x1 << 0 ) /* Endpoint 12 needs service */ 00156 #define UDC_UISR1_IR13 ( 0x1 << 0 ) /* Endpoint 13 needs service */ 00157 #define UDC_UISR1_IR14 ( 0x1 << 0 ) /* Endpoint 14 needs service */ 00158 #define UDC_UISR1_IR15 ( 0x1 << 0 ) /* Endpoint 15 needs service */ 00159 00160 /* UDC Frame Number High Register (UFNHR) */ 00161 #define UDC_UFNHR_FN_SHIFT 8 00162 #define UDC_UFNHR_FN_MASK ( 0x7 ) 00163 /* Used to read the 3 most significant bits of the 00164 * 11-bit frame numbe associated with last SOF 00165 */ 00166 #define UDC_UFNHR_SIM ( 0x1 << 6 ) /* SOF(start of frame) interrupt disabled */ 00167 #define UDC_UFNHR_SIR ( 0x1 << 7 ) /* SOF(start of frame) interrupt received */ 00168 00169 00170 /* UDC Frame Number Low Register (UFNLR) */ 00171 #define UDC_UFNLR_FN_MASK ( 0xff ) /* Used to read the 8 least significant bits of the 00172 * 11-bit frame number associated with last SOF 00173 */ 00174 00175 /* UDC Byte Count Register (UBCR) */ 00176 #define UDC_UBC_BYTECNT_MASK ( 0xff << 0 ) /* Used to read the number of bytes 00177 * remaining in the input buffer of 00178 * any endpoint 00179 */ 00180 00181 00182 /* UDC Endpoint Data Register (UDDR) */ 00183 00184 /* The Endpoint FIFOs are composed of 32 bit words of which only the lower 8 bits are used. 00185 Use this mask to ensure that FIFO reads and writes are not affected by the unused bits 8-31 */ 00186 #define UDC_UDDR_RW_MASK ( 0xff << 0 ) /* Used to read bottom of Endpoint 0 data 00187 * currently being loaded. Also used to 00188 * mask data to be written to top of 00189 * endpoint 0 data 00190 */ 00191 00192 00193 #define UDC_ENABLE_ALL_INT ( 0x0 ) /* Used to enable all int for EP0-7 and EP8-15 */ 00194 #define UDC_DISABLE_ALL_INT ( 0xff ) /* Used to disable all int for EP0-7 and EP8-15 */ 00195 #define UDC_CLEAR_ALL_INT ( 0xff ) /* Used to clear all intterupts for EP0-7 and EP8-15 */ 00196 #define UDC_DMA_ENABLED ( 0x1 ) /* Used to enable DMA transfer for Endpoint */ 00197 #define UDC_NO_DMA ( 0x0 ) /* Used to disable DMA transfer for Endpoint */ 00198 #define UDC_DME_SET ( 0x1 ) 00199 #define UDC_INT_MASKED ( 0x1 ) 00200 #define UDC_SETUP 0x81 /* Used to identify a Setup transaction */ 00201 #define UDC_TYPE_MASK (0x3 << 5) /* Used to identify a Request Type */ 00202 #define UDC_DIRECTION_MASK (0x1 << 7) /* Used to identify the transfer direction */ 00203 00204 #define HOST_TO_DEVICE 0 00205 #define DEVICE_TO_HOST 1 00206 00207 #define USB_DEVICE_CONTEXT_CHECK_PATTERN ( 0xff00aa33) /* Check pattern used to validate device contexts */ 00208 00209 #endif /* usbprivateconstants_H */ 00210 |
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Automatically generated from sources. © Intel Corp. 2003 |