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IxOsCacheMMU.h File Reference

this file contains the API of the component More...

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Defines

#define IxOsCacheMMU_H
#define IX_OS_CACHE_DOXYGEN
#define IX_ACC_CACHE_ENABLED
 This macro enable cached memory in Access layers.

#define IX_ACC_DRV_DMA_MALLOC(size)
 Allocate memory for driver use, that will be shared between XScale and NPE's.

#define IX_ACC_DRV_DMA_FREE(ptr, size)
 Free memory allocated from IX_ACC_DRV_DMA_MALLOC.

#define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION(addr)
 Return a virtual address for the provided physical address.

#define IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION(addr)
 Return a physical address for the provided virtual address.

#define IX_XSCALE_CACHE_LINE_SIZE
 IX_XSCALE_CACHE_LINE_SIZE = size of cache line for both flush and invalidate.

#define IX_ACC_DRAM_PHYS_OFFSET
 PHYS_OFFSET = Physical DRAM offset..

#define IX_ACC_DATA_CACHE_INVALIDATE(addr, size)
 Invalidate a cache range.

#define IX_ACC_DATA_CACHE_FLUSH(addr, size)
 Flush a cache range to physical memory.

#define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION(addr)
 Return a virtual address for the provided physical address.

#define IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION(addr)
 Return a physical address for the provided virtual address.

#define IX_ACC_DATA_CACHE_INVALIDATE(addr, size)
 Invalidate a cache range.

#define IX_ACC_DATA_CACHE_FLUSH(addr, size)
 Flush a cache range to physical memory.

#define IX_ACC_DRAM_PHYS_OFFSET
 PHYS_OFFSET = Physical DRAM offset..

#define IX_XSCALE_CACHE_LINE_SIZE
 IX_XSCALE_CACHE_LINE_SIZE = size of cache line for both flush and invalidate.

#define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION(addr)
 Return a virtual address for the provided physical address.

#define IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION(addr)
 Return a physical address for the provided virtual address.

#define IX_ACC_DATA_CACHE_INVALIDATE(addr, size)
 Invalidate a cache range.

#define IX_ACC_DATA_CACHE_FLUSH(addr, size)
 Flush a cache range to physical memory.

#define IX_XSCALE_CACHE_LINE_SIZE
 IX_XSCALE_CACHE_LINE_SIZE = size of cache line for both flush and invalidate.


Functions

void * ixOsServCacheDmaAlloc (UINT32 size)
 Allocate memory for driver use, that will be shared between XScale and NPE's.

void ixOsServCacheDmaFree (void *ptr, UINT32 size)
 Free memory allocated from ixOsServCacheDmaAlloc.


Detailed Description

this file contains the API of the component


Version:
Revision
1.33
-- Intel Copyright Notice --
Copyright 2002-2003 Intel Corporation All Rights Reserved.
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Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.
For further details, please see the file README.TXT distributed with this software.
-- End Intel Copyright Notice --

Definition in file IxOsCacheMMU.h.


Define Documentation

#define IX_ACC_DATA_CACHE_FLUSH addr,
size   ) 
 

Flush a cache range to physical memory.

Flush a cache range to physical memory.

Note:
This is typically done prior to submitting a buffer to the NPE's which you expect the NPE to read from. Entire Cache lines will be flushed.
  • If memory space used is non cached, then this function does may be null.
  • Functionality required:
    1. Non-Cached space : Flush CPU WB, No cache Flush.
    2. Write Through Enabled : Flush CPU WB, No cache Flush.
    3. Copy Back Enabled : Flush CPU WB, Invalidate area specified

Attention:
There are different implementations for this macro


Definition at line 364 of file IxOsCacheMMU.h.

#define IX_ACC_DATA_CACHE_FLUSH addr,
size   ) 
 

Flush a cache range to physical memory.

Flush a cache range to physical memory.

Note:
This is typically done prior to submitting a buffer to the NPE's which you expect the NPE to read from. Entire Cache lines will be flushed.
  • If memory space used is non cached, then this function does may be null.
  • Functionality required:
    1. Non-Cached space : Flush CPU WB, No cache Flush.
    2. Write Through Enabled : Flush CPU WB, No cache Flush.
    3. Copy Back Enabled : Flush CPU WB, Invalidate area specified

Attention:
There are different implementations for this macro


Definition at line 364 of file IxOsCacheMMU.h.

#define IX_ACC_DATA_CACHE_INVALIDATE addr,
size   ) 
 

Invalidate a cache range.

Invalidate a cache range.

Note:
This is typically done prior to submitting a buffer to the NPE's which you expect the NPE to populate with data.
Attention:
The size argument must be a multiple of cacheline size, i.e. a multiple if 32bytes for the XSCALE. The argument shall be rounded up to the next 32byte boundry. Extreem care must be taken when invalidating cache lines due.
  • If memory space used is non cached, then this function may be null.
  • Functionality required:
    1. Non-Cached space : No functionality required.
    2. Write Through Enabled : Invalidate area specified
    3. Copy Back Enabled : Invalidate area specified

Attention:
There are different implementations for this macro


Definition at line 363 of file IxOsCacheMMU.h.

#define IX_ACC_DATA_CACHE_INVALIDATE addr,
size   ) 
 

Invalidate a cache range.

Invalidate a cache range.

Note:
This is typically done prior to submitting a buffer to the NPE's which you expect the NPE to populate with data.
Attention:
The size argument must be a multiple of cacheline size, i.e. a multiple if 32bytes for the XSCALE. The argument shall be rounded up to the next 32byte boundry. Extreem care must be taken when invalidating cache lines due.
  • If memory space used is non cached, then this function may be null.
  • Functionality required:
    1. Non-Cached space : No functionality required.
    2. Write Through Enabled : Invalidate area specified
    3. Copy Back Enabled : Invalidate area specified

Attention:
There are different implementations for this macro


Definition at line 363 of file IxOsCacheMMU.h.

#define IX_ACC_DRAM_PHYS_OFFSET
 

PHYS_OFFSET = Physical DRAM offset..

Attention:
There are different implementations for this macro
  • Linux OS implementation:
    • #define IX_ACC_DRAM_PHYS_OFFSET (PHYS_OFFSET)

  • VxWorks OS implementation:
    • #define IX_ACC_DRAM_PHYS_OFFSET (0x00000000UL)


Definition at line 352 of file IxOsCacheMMU.h.

#define IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION addr   ) 
 

Return a physical address for the provided virtual address.

This macro return a physical address for the provided virtual address

Attention:
There are different implementations for this macro


Definition at line 362 of file IxOsCacheMMU.h.

#define IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION addr   ) 
 

Return a physical address for the provided virtual address.

This macro return a physical address for the provided virtual address

Attention:
There are different implementations for this macro


Definition at line 362 of file IxOsCacheMMU.h.

#define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION addr   ) 
 

Return a virtual address for the provided physical address.

This macro return a virtual address for the provided physical address.

Attention:
There are different implementations for this macro


Definition at line 361 of file IxOsCacheMMU.h.

#define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION addr   ) 
 

Return a virtual address for the provided physical address.

This macro return a virtual address for the provided physical address.

Attention:
There are different implementations for this macro


Definition at line 361 of file IxOsCacheMMU.h.

#define IX_XSCALE_CACHE_LINE_SIZE
 

IX_XSCALE_CACHE_LINE_SIZE = size of cache line for both flush and invalidate.


Definition at line 366 of file IxOsCacheMMU.h.

#define IX_XSCALE_CACHE_LINE_SIZE
 

IX_XSCALE_CACHE_LINE_SIZE = size of cache line for both flush and invalidate.


Definition at line 366 of file IxOsCacheMMU.h.

Automatically generated from sources. © Intel Corp. 2003