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IxNpeA.h

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00001 
00057 #ifndef IX_NPE_A_H
00058 #define IX_NPE_A_H
00059 
00060 #include "IxTypes.h"
00061 #include "IxOsBuffMgt.h"
00062 
00063 /* General Message Ids */
00064 
00065 /* ATM Message Ids */
00066 
00073 #define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE       0x20
00074 
00081 #define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD        0x21
00082 
00089 #define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD      0x22
00090 
00097 #define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ        0x23
00098 
00107 #define IX_NPE_A_MSSG_ATM_TX_ENABLE                 0x25
00108 
00117 #define IX_NPE_A_MSSG_ATM_TX_DISABLE                0x26
00118 
00128 #define IX_NPE_A_MSSG_ATM_RX_ENABLE                 0x27
00129 
00138 #define IX_NPE_A_MSSG_ATM_RX_DISABLE                0x28
00139 
00146 #define IX_NPE_A_MSSG_ATM_STATUS_READ               0x29
00147 
00148 /*--------------------------------------------------------------------------
00149  * HSS Message IDs
00150  *--------------------------------------------------------------------------*/
00151 
00158 #define IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE         0x40
00159 
00167 #define IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD          0x41
00168 
00175 #define IX_NPE_A_MSSG_HSS_PORT_ERROR_READ           0x42
00176 
00183 #define IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE          0x43
00184 
00191 #define IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE         0x44
00192 
00199 #define IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE   0x45
00200 
00207 #define IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE      0x46
00208 
00215 #define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE    0x47
00216 
00223 #define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE     0x48
00224 
00232 #define IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE     0x49
00233 
00239 #define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE    0x4A
00240 
00247 #define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE    0x4B
00248 
00256 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE      0x50
00257 
00263 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE     0x51
00264 
00270 #define IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE       0x52
00271 
00278 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE 0x53
00279 
00287 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE   0x54
00288 
00295 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE 0x55
00296 
00303 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE    0x56
00304 
00311 #define IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE       0x57
00312 
00313 
00314 
00315 /* Queue Entry Masks */
00316 
00317 /*--------------------------------------------------------------------------
00318  *  ATM Descriptor Structure offsets
00319  *--------------------------------------------------------------------------*/
00320 
00328 #define IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET          0
00329 
00337 #define IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET            1
00338 
00347 #define IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET    2
00348 
00354 #define IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET       4
00355 
00365 #define IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET    12
00366 
00374 #define IX_NPE_A_RXDESCRIPTOR_TIMELIMIT_OFFSET        14
00375 
00383 #define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET     20
00384 
00392 #define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET  24
00393 
00401 #define IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET      28
00402 
00410 #define IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET    32
00411 
00419 #define IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 36
00420 
00428 #define IX_NPE_A_RXDESCRIPTOR_SIZE                  40
00429 
00437 #define IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET            0
00438 
00444 #define IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET            1
00445 
00455 #define IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET     2
00456 
00461 #define IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET       4
00462 
00468 #define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET      8
00469 
00477 #define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET  12
00478 
00484 #define IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET      16
00485 
00493 #define IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET    20
00494 
00502 #define IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 24
00503 
00509 #define IX_NPE_A_TXDESCRIPTOR_SIZE                  28
00510 
00511 /* Global compiler switch to select between 3 possible NPE Modes */
00512 /* Default(No Switch) = MultiPHY Utopia2 */
00513 /* IX_UTOPIAMODE=1 for single Phy Utopia1 */
00514 /* IX_MPHYSINGLEPORT=1 for single Phy Utopia2 */
00516 #define IX_NPE_MPHYMULTIPORT 1
00517 #if IX_UTOPIAMODE == 1
00518 #undef  IX_NPE_MPHYMULTIPORT
00519 #endif
00520 #if IX_MPHYSINGLEPORT == 1
00521 #undef  IX_NPE_MPHYMULTIPORT
00522 #endif
00523 /*--------------------------------------------------------------------------
00524  *  Hardware queue IDs relating to Atm Part-I
00525  *--------------------------------------------------------------------------*/
00526 
00532 #define IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK  2
00533 
00539 #define IX_NPE_A_QMQ_ATM_TX_DONE       1
00540 
00546 #define IX_NPE_A_QMQ_ATM_TX0           2
00547 
00548 
00572 #ifdef IX_NPE_MPHYMULTIPORT
00573 
00578 #define IX_NPE_A_QMQ_ATM_TX1           IX_NPE_A_QMQ_ATM_TX0+1
00579 #define IX_NPE_A_QMQ_ATM_TX2           IX_NPE_A_QMQ_ATM_TX1+1
00580 #define IX_NPE_A_QMQ_ATM_TX3           IX_NPE_A_QMQ_ATM_TX2+1
00581 #define IX_NPE_A_QMQ_ATM_TX4           IX_NPE_A_QMQ_ATM_TX3+1
00582 #define IX_NPE_A_QMQ_ATM_TX5           IX_NPE_A_QMQ_ATM_TX4+1
00583 #define IX_NPE_A_QMQ_ATM_TX6           IX_NPE_A_QMQ_ATM_TX5+1
00584 #define IX_NPE_A_QMQ_ATM_TX7           IX_NPE_A_QMQ_ATM_TX6+1
00585 #define IX_NPE_A_QMQ_ATM_TX8           IX_NPE_A_QMQ_ATM_TX7+1
00586 #define IX_NPE_A_QMQ_ATM_TX9           IX_NPE_A_QMQ_ATM_TX8+1
00587 #define IX_NPE_A_QMQ_ATM_TX10          IX_NPE_A_QMQ_ATM_TX9+1
00588 #define IX_NPE_A_QMQ_ATM_TX11          IX_NPE_A_QMQ_ATM_TX10+1
00589 #define IX_NPE_A_QMQ_ATM_TXID_MIN      IX_NPE_A_QMQ_ATM_TX0
00590 #define IX_NPE_A_QMQ_ATM_TXID_MAX      IX_NPE_A_QMQ_ATM_TX11
00591 #define IX_NPE_A_QMQ_ATM_RX_HI         21
00592 #define IX_NPE_A_QMQ_ATM_RX_LO         22
00593 #else
00594 #define IX_NPE_A_QMQ_ATM_TXID_MIN      IX_NPE_A_QMQ_ATM_TX0
00595 #define IX_NPE_A_QMQ_ATM_TXID_MAX      IX_NPE_A_QMQ_ATM_TX0
00596 #define IX_NPE_A_QMQ_ATM_RX_HI         10
00597 #define IX_NPE_A_QMQ_ATM_RX_LO         11
00598 #endif /* MPHY */
00599 
00600 /*--------------------------------------------------------------------------
00601  * Hardware queue IDs relating to HSS Port 0
00602  *--------------------------------------------------------------------------*/
00603 
00609 #define IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG   12
00610 
00616 #define IX_NPE_A_QMQ_HSS0_PKT_RX        13
00617 
00623 #define IX_NPE_A_QMQ_HSS0_PKT_TX0       14
00624 
00630 #define IX_NPE_A_QMQ_HSS0_PKT_TX1       15
00631 
00637 #define IX_NPE_A_QMQ_HSS0_PKT_TX2       16
00638 
00644 #define IX_NPE_A_QMQ_HSS0_PKT_TX3       17
00645 
00651 #define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0  18
00652 
00658 #define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1  19
00659 
00665 #define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2  20
00666 
00672 #define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3  21
00673 
00679 #define IX_NPE_A_QMQ_HSS0_PKT_TX_DONE   22
00680 
00681 
00682 /*--------------------------------------------------------------------------
00683  * Hardware queue IDs relating to HSS Port 1
00684  *--------------------------------------------------------------------------*/
00685 
00691 #define IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG   10
00692 
00698 #define IX_NPE_A_QMQ_HSS1_PKT_RX        0
00699 
00705 #define IX_NPE_A_QMQ_HSS1_PKT_TX0       5
00706 
00712 #define IX_NPE_A_QMQ_HSS1_PKT_TX1       6
00713 
00719 #define IX_NPE_A_QMQ_HSS1_PKT_TX2       7
00720 
00726 #define IX_NPE_A_QMQ_HSS1_PKT_TX3       8
00727 
00733 #define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0  1
00734 
00740 #define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1  2
00741 
00747 #define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2  3
00748 
00754 #define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3  4
00755 
00761 #define IX_NPE_A_QMQ_HSS1_PKT_TX_DONE   9
00762 
00763 /*--------------------------------------------------------------------------
00764  * Hardware queue IDs relating to Atm Part-II
00765  *--------------------------------------------------------------------------*/
00766 
00775 #define IX_NPE_A_QMQ_ATM_FREE_VC0      32
00776 #define IX_NPE_A_QMQ_ATM_FREE_VC1      IX_NPE_A_QMQ_ATM_FREE_VC0+1
00777 #define IX_NPE_A_QMQ_ATM_FREE_VC2      IX_NPE_A_QMQ_ATM_FREE_VC1+1
00778 #define IX_NPE_A_QMQ_ATM_FREE_VC3      IX_NPE_A_QMQ_ATM_FREE_VC2+1
00779 #define IX_NPE_A_QMQ_ATM_FREE_VC4      IX_NPE_A_QMQ_ATM_FREE_VC3+1
00780 #define IX_NPE_A_QMQ_ATM_FREE_VC5      IX_NPE_A_QMQ_ATM_FREE_VC4+1
00781 #define IX_NPE_A_QMQ_ATM_FREE_VC6      IX_NPE_A_QMQ_ATM_FREE_VC5+1
00782 #define IX_NPE_A_QMQ_ATM_FREE_VC7      IX_NPE_A_QMQ_ATM_FREE_VC6+1
00783 #define IX_NPE_A_QMQ_ATM_FREE_VC8      IX_NPE_A_QMQ_ATM_FREE_VC7+1
00784 #define IX_NPE_A_QMQ_ATM_FREE_VC9      IX_NPE_A_QMQ_ATM_FREE_VC8+1
00785 #define IX_NPE_A_QMQ_ATM_FREE_VC10     IX_NPE_A_QMQ_ATM_FREE_VC9+1
00786 #define IX_NPE_A_QMQ_ATM_FREE_VC11     IX_NPE_A_QMQ_ATM_FREE_VC10+1
00787 #define IX_NPE_A_QMQ_ATM_FREE_VC12     IX_NPE_A_QMQ_ATM_FREE_VC11+1
00788 #define IX_NPE_A_QMQ_ATM_FREE_VC13     IX_NPE_A_QMQ_ATM_FREE_VC12+1
00789 #define IX_NPE_A_QMQ_ATM_FREE_VC14     IX_NPE_A_QMQ_ATM_FREE_VC13+1
00790 #define IX_NPE_A_QMQ_ATM_FREE_VC15     IX_NPE_A_QMQ_ATM_FREE_VC14+1
00791 #define IX_NPE_A_QMQ_ATM_FREE_VC16     IX_NPE_A_QMQ_ATM_FREE_VC15+1
00792 #define IX_NPE_A_QMQ_ATM_FREE_VC17     IX_NPE_A_QMQ_ATM_FREE_VC16+1
00793 #define IX_NPE_A_QMQ_ATM_FREE_VC18     IX_NPE_A_QMQ_ATM_FREE_VC17+1
00794 #define IX_NPE_A_QMQ_ATM_FREE_VC19     IX_NPE_A_QMQ_ATM_FREE_VC18+1
00795 #define IX_NPE_A_QMQ_ATM_FREE_VC20     IX_NPE_A_QMQ_ATM_FREE_VC19+1
00796 #define IX_NPE_A_QMQ_ATM_FREE_VC21     IX_NPE_A_QMQ_ATM_FREE_VC20+1
00797 #define IX_NPE_A_QMQ_ATM_FREE_VC22     IX_NPE_A_QMQ_ATM_FREE_VC21+1
00798 #define IX_NPE_A_QMQ_ATM_FREE_VC23     IX_NPE_A_QMQ_ATM_FREE_VC22+1
00799 #define IX_NPE_A_QMQ_ATM_FREE_VC24     IX_NPE_A_QMQ_ATM_FREE_VC23+1
00800 #define IX_NPE_A_QMQ_ATM_FREE_VC25     IX_NPE_A_QMQ_ATM_FREE_VC24+1
00801 #define IX_NPE_A_QMQ_ATM_FREE_VC26     IX_NPE_A_QMQ_ATM_FREE_VC25+1
00802 #define IX_NPE_A_QMQ_ATM_FREE_VC27     IX_NPE_A_QMQ_ATM_FREE_VC26+1
00803 #define IX_NPE_A_QMQ_ATM_FREE_VC28     IX_NPE_A_QMQ_ATM_FREE_VC27+1
00804 #define IX_NPE_A_QMQ_ATM_FREE_VC29     IX_NPE_A_QMQ_ATM_FREE_VC28+1
00805 #define IX_NPE_A_QMQ_ATM_FREE_VC30     IX_NPE_A_QMQ_ATM_FREE_VC29+1
00806 #define IX_NPE_A_QMQ_ATM_FREE_VC31     IX_NPE_A_QMQ_ATM_FREE_VC30+1
00807 
00813 #define IX_NPE_A_QMQ_ATM_RXFREE_MIN  IX_NPE_A_QMQ_ATM_FREE_VC0
00814 
00820 #define IX_NPE_A_QMQ_ATM_RXFREE_MAX  IX_NPE_A_QMQ_ATM_FREE_VC31
00821 
00826 #ifdef IX_NPE_MPHYMULTIPORT
00827 #define IX_NPE_A_QMQ_OAM_FREE_VC       14
00828 #else
00829 #define IX_NPE_A_QMQ_OAM_FREE_VC       3
00830 #endif
00831 
00837 #define IX_NPE_A_CHAIN_DESC_COUNT_MAX            256
00838 
00839 
00840 
00841 /*
00842  *  Definition of the ATM cell header
00843  *
00844  * This would most conviently be defined as the bit field shown below.
00845  * Endian portability prevents this, therefore a set of macros
00846  * are defined to access the fields within the cell header assumed to
00847  * be passed as a UINT32.
00848  *
00849  * Changes to field sizes or orders must be reflected in the offset
00850  * definitions above.
00851  *
00852  *    typedef struct
00853  *    {
00854  *       unsigned int gfc:4;
00855  *       unsigned int vpi:8;
00856  *       unsigned int vci:16;
00857  *       unsigned int pti:3;
00858  *       unsigned int clp:1;
00859  *    } IxNpeA_AtmCellHeader;
00860  *
00861  */
00862 
00864 #define GFC_MASK        0xf0000000
00865 
00867 #define IX_NPE_A_ATMCELLHEADER_GFC_GET( header ) \
00868 (((header) & GFC_MASK) >> 28)
00869 
00871 #define IX_NPE_A_ATMCELLHEADER_GFC_SET( header,gfc ) \
00872 do { \
00873     (header) &= ~GFC_MASK; \
00874     (header) |= (((gfc) << 28) & GFC_MASK); \
00875 } while(0)
00876 
00878 #define VPI_MASK        0x0ff00000
00879 
00881 #define IX_NPE_A_ATMCELLHEADER_VPI_GET( header ) \
00882 (((header) & VPI_MASK) >> 20)
00883 
00885 #define IX_NPE_A_ATMCELLHEADER_VPI_SET( header, vpi ) \
00886 do { \
00887     (header) &= ~VPI_MASK; \
00888     (header) |= (((vpi) << 20) & VPI_MASK); \
00889 } while(0)
00890 
00892 #define VCI_MASK        0x000ffff0
00893 
00895 #define IX_NPE_A_ATMCELLHEADER_VCI_GET( header ) \
00896 (((header) & VCI_MASK) >> 4)
00897 
00899 #define IX_NPE_A_ATMCELLHEADER_VCI_SET( header, vci ) \
00900 do { \
00901     (header) &= ~VCI_MASK; \
00902     (header) |= (((vci) << 4) & VCI_MASK); \
00903 } while(0)
00904 
00906 #define PTI_MASK        0x0000000e
00907 
00909 #define IX_NPE_A_ATMCELLHEADER_PTI_GET( header ) \
00910 (((header) & PTI_MASK) >> 1)
00911 
00913 #define IX_NPE_A_ATMCELLHEADER_PTI_SET( header, pti ) \
00914 do { \
00915     (header) &= ~PTI_MASK; \
00916     (header) |= (((pti) << 1) & PTI_MASK); \
00917 } while(0)
00918 
00920 #define CLP_MASK        0x00000001
00921 
00923 #define IX_NPE_A_ATMCELLHEADER_CLP_GET( header ) \
00924 ((header) & CLP_MASK)
00925 
00927 #define IX_NPE_A_ATMCELLHEADER_CLP_SET( header, clp ) \
00928 do { \
00929     (header) &= ~CLP_MASK; \
00930     (header) |= ((clp) & CLP_MASK); \
00931 } while(0)
00932 
00933 
00934 /*
00935 * Definition of the Rx bitfield
00936 *
00937 * This would most conviently be defined as the bit field shown below.
00938 * Endian portability prevents this, therefore a set of macros
00939 * are defined to access the fields within the rxBitfield assumed to
00940 * be passed as a UINT32.
00941 *
00942 * Changes to field sizes or orders must be reflected in the offset
00943 * definitions above.
00944 *
00945 * Rx bitfield
00946 *    struct
00947 *    {   IX_NPEA_RXBITFIELD(
00948 *        unsigned int status:1,
00949 *        unsigned int port:7,
00950 *        unsigned int vcId:8,
00951 *        unsigned int currMbufSize:16);
00952 *    } rxBitField;
00953 *
00954 */
00955 
00957 #define STATUS_MASK     0x80000000
00958 
00960 #define IX_NPE_A_RXBITFIELD_STATUS_GET( rxbitfield ) \
00961 (((rxbitfield) & STATUS_MASK) >> 31)
00962 
00964 #define IX_NPE_A_RXBITFIELD_STATUS_SET( rxbitfield, status ) \
00965 do { \
00966     (rxbitfield) &= ~STATUS_MASK; \
00967     (rxbitfield) |= (((status) << 31) & STATUS_MASK); \
00968 } while(0)
00969 
00971 #define PORT_MASK       0x7f000000
00972 
00974 #define IX_NPE_A_RXBITFIELD_PORT_GET( rxbitfield ) \
00975 (((rxbitfield) & PORT_MASK) >> 24)
00976 
00978 #define IX_NPE_A_RXBITFIELD_PORT_SET( rxbitfield, port ) \
00979 do { \
00980     (rxbitfield) &= ~PORT_MASK; \
00981     (rxbitfield) |= (((port) << 24) & PORT_MASK); \
00982 } while(0)
00983 
00985 #define VCID_MASK       0x00ff0000
00986 
00988 #define IX_NPE_A_RXBITFIELD_VCID_GET( rxbitfield ) \
00989 (((rxbitfield) & VCID_MASK) >> 16)
00990 
00992 #define IX_NPE_A_RXBITFIELD_VCID_SET( rxbitfield, vcid ) \
00993 do { \
00994     (rxbitfield) &= ~VCID_MASK; \
00995     (rxbitfield) |= (((vcid) << 16) & VCID_MASK); \
00996 } while(0)
00997 
00999 #define CURRMBUFSIZE_MASK       0x0000ffff
01000 
01002 #define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET( rxbitfield ) \
01003 ((rxbitfield) & CURRMBUFSIZE_MASK)
01004 
01006 #define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET( rxbitfield, currmbufsize ) \
01007 do { \
01008     (rxbitfield) &= ~CURRMBUFSIZE_MASK; \
01009     (rxbitfield) |= ((currmbufsize) & CURRMBUFSIZE_MASK); \
01010 } while(0)
01011 
01012 
01013 
01017 typedef struct
01018 {
01019     UINT8 port;             
01020     UINT8 aalType;          
01021     UINT16 currMbufLen;         
01022     UINT32 atmCellHeader;       
01023     IX_MBUF *pCurrMbuf;         
01024     unsigned char *pCurrMbufData;   
01025     IX_MBUF *pNextMbuf;         
01026     UINT32  totalLen;           
01027     UINT32  aal5CrcResidue;     
01028 } IxNpeA_TxAtmVc;
01029 
01030 /* Changes to field sizes or orders must be reflected in the offset
01031  * definitions above. */
01032 
01033 
01034 
01035 
01039 typedef struct
01040 {
01041     UINT32  rxBitField;         
01042     UINT32  atmCellHeader;      
01043     UINT32  rsvdWord0;                  
01044     UINT16  currMbufLen;        
01045     UINT8   timeLimit;          
01046     UINT8   rsvdByte0;                  
01047     UINT32  rsvdWord1;          
01048     IX_MBUF *pCurrMbuf;         
01049     unsigned char *pCurrMbufData;   
01050     IX_MBUF *pNextMbuf;         
01051     UINT32  totalLen;           
01052     UINT32  aal5CrcResidue;     
01053 } IxNpeA_RxAtmVc;
01054 
01055 
01059 typedef enum
01060 {
01061     IX_NPE_A_AAL_TYPE_INVALID = 0,  
01062     IX_NPE_A_AAL_TYPE_0_48    = 0x1,    
01063     IX_NPE_A_AAL_TYPE_0_52    = 0x2,    
01064     IX_NPE_A_AAL_TYPE_5       = 0x5,    
01065     IX_NPE_A_AAL_TYPE_OAM     = 0xF 
01066 } IxNpeA_AalType;
01067 
01071 typedef enum
01072 {
01073     IX_NPE_A_52_BYTE_PAYLOAD = 0,   
01074     IX_NPE_A_48_BYTE_PAYLOAD        
01075 } IxNpeA_PayloadFormat;
01076 
01080 typedef struct
01081 {
01082     UINT8   status;     
01083     UINT8   errorCount;     
01084     UINT8   chainCount;     
01085     UINT8   rsvdByte0;      
01087     UINT16  packetLength;   
01088     UINT16  rsvdShort0;     
01090     IX_MBUF *pRootMbuf;     
01091     IX_MBUF *pNextMbuf;     
01092     UINT8   *pMbufData;     
01093     UINT32  mbufLength;     
01095 } IxNpeA_NpePacketDescriptor;
01096 
01097 
01098 #endif
01099 
Automatically generated from sources. © Intel Corp. 2003