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00090 #ifndef IXHSSACC_H
00091 #define IXHSSACC_H
00092
00093 #include "IxTypes.h"
00094 #include "IxOsBuffMgt.h"
00095
00096
00097
00098
00099
00106 #define IX_HSSACC_TSLOTS_PER_HSS_PORT 128
00107
00108
00109
00110
00111
00112
00118 #define IX_HSSACC_PARAM_ERR 2
00119
00125 #define IX_HSSACC_RESOURCE_ERR 3
00126
00133 #define IX_HSSACC_PKT_DISCONNECTING 4
00134
00141 #define IX_HSSACC_Q_WRITE_OVERFLOW 5
00142
00143
00144
00145
00151 #define IX_HSSACC_NO_ERROR 0
00152
00158 #define IX_HSSACC_TX_FRM_SYNC_ERR 1
00159
00165 #define IX_HSSACC_TX_OVER_RUN_ERR 2
00166
00172 #define IX_HSSACC_CHANNELISED_SW_TX_ERR 3
00173
00179 #define IX_HSSACC_PACKETISED_SW_TX_ERR 4
00180
00186 #define IX_HSSACC_RX_FRM_SYNC_ERR 5
00187
00193 #define IX_HSSACC_RX_OVER_RUN_ERR 6
00194
00200 #define IX_HSSACC_CHANNELISED_SW_RX_ERR 7
00201
00207 #define IX_HSSACC_PACKETISED_SW_RX_ERR 8
00208
00209
00210
00211
00212
00219 #define IX_HSSACC_PKT_MIN_RX_MBUF_SIZE 64
00220
00221
00222
00223
00224
00230 typedef enum
00231 {
00232 IX_HSSACC_HSS_PORT_0,
00233 IX_HSSACC_HSS_PORT_1,
00234 IX_HSSACC_HSS_PORT_MAX
00235 } IxHssAccHssPort;
00236
00243 typedef enum
00244 {
00245 IX_HSSACC_HDLC_PORT_0,
00246 IX_HSSACC_HDLC_PORT_1,
00247 IX_HSSACC_HDLC_PORT_2,
00248 IX_HSSACC_HDLC_PORT_3,
00249 IX_HSSACC_HDLC_PORT_MAX
00250 } IxHssAccHdlcPort;
00251
00257 typedef enum
00258 {
00259 IX_HSSACC_TDMMAP_UNASSIGNED,
00260 IX_HSSACC_TDMMAP_HDLC,
00261 IX_HSSACC_TDMMAP_VOICE56K,
00262 IX_HSSACC_TDMMAP_VOICE64K,
00263 IX_HSSACC_TDMMAP_MAX
00264 } IxHssAccTdmSlotUsage;
00265
00271 typedef enum
00272 {
00273 IX_HSSACC_FRM_SYNC_ACTIVE_LOW,
00274 IX_HSSACC_FRM_SYNC_ACTIVE_HIGH,
00275 IX_HSSACC_FRM_SYNC_FALLINGEDGE,
00276 IX_HSSACC_FRM_SYNC_RISINGEDGE,
00277 IX_HSSACC_FRM_SYNC_TYPE_MAX
00278 } IxHssAccFrmSyncType;
00279
00285 typedef enum
00286 {
00287 IX_HSSACC_FRM_SYNC_INPUT,
00288 IX_HSSACC_FRM_SYNC_INVALID_VALUE,
00289 IX_HSSACC_FRM_SYNC_OUTPUT_FALLING,
00291 IX_HSSACC_FRM_SYNC_OUTPUT_RISING,
00293 IX_HSSACC_FRM_SYNC_ENABLE_MAX
00294 } IxHssAccFrmSyncEnable;
00295
00302 typedef enum
00303 {
00304 IX_HSSACC_CLK_EDGE_FALLING,
00305 IX_HSSACC_CLK_EDGE_RISING,
00306 IX_HSSACC_CLK_EDGE_MAX
00307 } IxHssAccClkEdge;
00308
00314 typedef enum
00315 {
00316 IX_HSSACC_SYNC_CLK_DIR_INPUT,
00317 IX_HSSACC_SYNC_CLK_DIR_OUTPUT,
00318 IX_HSSACC_SYNC_CLK_DIR_MAX
00319 } IxHssAccClkDir;
00320
00326 typedef enum
00327 {
00328 IX_HSSACC_FRM_PULSE_ENABLED,
00329 IX_HSSACC_FRM_PULSE_DISABLED,
00330 IX_HSSACC_FRM_PULSE_MAX
00331 } IxHssAccFrmPulseUsage;
00332
00338 typedef enum
00339 {
00340 IX_HSSACC_CLK_RATE,
00341 IX_HSSACC_HALF_CLK_RATE,
00342 IX_HSSACC_DATA_RATE_MAX
00343 } IxHssAccDataRate;
00344
00350 typedef enum
00351 {
00352 IX_HSSACC_DATA_POLARITY_SAME,
00354 IX_HSSACC_DATA_POLARITY_INVERT,
00356 IX_HSSACC_DATA_POLARITY_MAX
00357 } IxHssAccDataPolarity;
00358
00364 typedef enum
00365 {
00366 IX_HSSACC_LSB_ENDIAN,
00367 IX_HSSACC_MSB_ENDIAN,
00368 IX_HSSACC_ENDIAN_MAX
00369 } IxHssAccBitEndian;
00370
00371
00377 typedef enum
00378 {
00379 IX_HSSACC_TX_PINS_NORMAL,
00380 IX_HSSACC_TX_PINS_OPEN_DRAIN,
00381 IX_HSSACC_TX_PINS_MAX
00382 } IxHssAccDrainMode;
00383
00389 typedef enum
00390 {
00391 IX_HSSACC_SOF_FBIT,
00392 IX_HSSACC_SOF_DATA,
00393 IX_HSSACC_SOF_MAX
00394 } IxHssAccSOFType;
00395
00402 typedef enum
00403 {
00404 IX_HSSACC_DE_TRI_STATE,
00405 IX_HSSACC_DE_DATA,
00406 IX_HSSACC_DE_MAX
00407 } IxHssAccDataEnable;
00408
00414 typedef enum
00415 {
00416 IX_HSSACC_TXSIG_LOW,
00417 IX_HSSACC_TXSIG_HIGH,
00418 IX_HSSACC_TXSIG_HIGH_IMP,
00419 IX_HSSACC_TXSIG_MAX
00420 } IxHssAccTxSigType;
00421
00429 typedef enum
00430 {
00431 IX_HSSACC_FB_FIFO,
00432 IX_HSSACC_FB_HIGH_IMP,
00433 IX_HSSACC_FB_MAX
00434 } IxHssAccFbType;
00435
00441 typedef enum
00442 {
00443 IX_HSSACC_56KE_BIT_7_UNUSED,
00444 IX_HSSACC_56KE_BIT_0_UNUSED,
00445 IX_HSSACC_56KE_MAX
00446 } IxHssAcc56kEndianness;
00447
00453 typedef enum
00454 {
00455 IX_HSSACC_56KS_32_8_DATA,
00456 IX_HSSACC_56KS_56K_DATA,
00457 IX_HSSACC_56KS_MAX
00458 } IxHssAcc56kSel;
00459
00460
00466 typedef enum
00467 {
00468 IX_HSSACC_CLK_SPEED_512KHZ,
00469 IX_HSSACC_CLK_SPEED_1536KHZ,
00470 IX_HSSACC_CLK_SPEED_1544KHZ,
00471 IX_HSSACC_CLK_SPEED_1568KHZ,
00472 IX_HSSACC_CLK_SPEED_2048KHZ,
00473 IX_HSSACC_CLK_SPEED_4096KHZ,
00474 IX_HSSACC_CLK_SPEED_8192KHZ,
00475 IX_HSSACC_CLK_SPEED_MAX
00476 } IxHssAccClkSpeed;
00477
00483 typedef enum
00484 {
00485 IX_HSSACC_PKT_OK,
00486 IX_HSSACC_STOP_SHUTDOWN_ERROR,
00488 IX_HSSACC_HDLC_ALN_ERROR,
00489 IX_HSSACC_HDLC_FCS_ERROR,
00490 IX_HSSACC_RXFREE_Q_EMPTY_ERROR,
00492 IX_HSSACC_HDLC_MAX_FRAME_SIZE_EXCEEDED,
00495 IX_HSSACC_HDLC_ABORT_ERROR,
00497 IX_HSSACC_DISCONNECT_IN_PROGRESS
00499 } IxHssAccPktStatus;
00500
00501
00507 typedef enum
00508 {
00509 IX_HSSACC_PKT_16_BIT_CRC = 16,
00510 IX_HSSACC_PKT_32_BIT_CRC = 32
00511 } IxHssAccPktCrcType;
00512
00518 typedef enum
00519 {
00520 IX_HSSACC_HDLC_IDLE_ONES,
00521 IX_HSSACC_HDLC_IDLE_FLAGS
00522 } IxHssAccPktHdlcIdleType;
00523
00530 typedef struct
00531 {
00532 IxHssAccFrmSyncType frmSyncType;
00533 IxHssAccFrmSyncEnable frmSyncIO;
00535 IxHssAccClkEdge frmSyncClkEdge;
00537 IxHssAccClkEdge dataClkEdge;
00538 IxHssAccClkDir clkDirection;
00539 IxHssAccFrmPulseUsage frmPulseUsage;
00541 IxHssAccDataRate dataRate;
00543 IxHssAccDataPolarity dataPolarity;
00544 IxHssAccBitEndian dataEndianness;
00545 IxHssAccDrainMode drainMode;
00546 IxHssAccSOFType fBitUsage;
00547 IxHssAccDataEnable dataEnable;
00549 IxHssAccTxSigType voice56kType;
00551 IxHssAccTxSigType unassignedType;
00553 IxHssAccFbType fBitType;
00554 IxHssAcc56kEndianness voice56kEndian;
00556 IxHssAcc56kSel voice56kSel;
00558 unsigned frmOffset;
00560 unsigned maxFrmSize;
00562 } IxHssAccPortConfig;
00563
00568 typedef struct
00569 {
00570 IxHssAccPortConfig txPortConfig;
00571 IxHssAccPortConfig rxPortConfig;
00572 unsigned numChannelised;
00574 unsigned hssPktChannelCount;
00576 UINT8 channelisedIdlePattern;
00579 BOOL loopback;
00580 unsigned packetizedIdlePattern;
00583 IxHssAccClkSpeed clkSpeed;
00584 } IxHssAccConfigParams;
00585
00590 typedef struct
00591 {
00592 BOOL hdlc56kMode;
00593 IxHssAcc56kEndianness hdlc56kEndian;
00595 BOOL hdlc56kUnusedBitPolarity0;
00598 } IxHssAccHdlcMode;
00599
00605 typedef struct
00606 {
00607 IxHssAccPktHdlcIdleType hdlcIdleType;
00608 IxHssAccBitEndian dataEndian;
00609 IxHssAccPktCrcType crcType;
00610 } IxHssAccPktHdlcFraming;
00611
00623 typedef UINT32 IxHssAccPktUserId;
00624
00625
00646 typedef void (*IxHssAccLastErrorCallback) (unsigned lastHssError,
00647 unsigned servicePort);
00648
00670 typedef void (*IxHssAccPktRxCallback) (IX_MBUF *buffer,
00671 unsigned numHssErrs,
00672 IxHssAccPktStatus pktStatus,
00673 IxHssAccPktUserId rxUserId);
00674
00689 typedef void (*IxHssAccPktRxFreeLowCallback) (IxHssAccPktUserId rxFreeLowUserId);
00690
00711 typedef void (*IxHssAccPktTxDoneCallback) (IX_MBUF *buffer,
00712 unsigned numHssErrs,
00713 IxHssAccPktStatus pktStatus,
00714 IxHssAccPktUserId txDoneUserId);
00715
00737 typedef void (*IxHssAccChanRxCallback) (IxHssAccHssPort hssPortId,
00738 unsigned rxOffset,
00739 unsigned txOffset,
00740 unsigned numHssErrs);
00741
00742
00743
00744
00745
00773 PUBLIC IX_STATUS
00774 ixHssAccPortInit (IxHssAccHssPort hssPortId,
00775 IxHssAccConfigParams *configParams,
00776 IxHssAccTdmSlotUsage *tdmMap,
00777 IxHssAccLastErrorCallback lastHssErrorCallback);
00778
00797 PUBLIC IX_STATUS
00798 ixHssAccLastErrorRetrievalInitiate (IxHssAccHssPort hssPortId);
00799
00800
00819 PUBLIC IX_STATUS
00820 ixHssAccInit (void);
00821
00822
00893 PUBLIC IX_STATUS
00894 ixHssAccPktPortConnect (IxHssAccHssPort hssPortId,
00895 IxHssAccHdlcPort hdlcPortId,
00896 BOOL hdlcFraming,
00897 IxHssAccHdlcMode hdlcMode,
00898 BOOL hdlcBitInvert,
00899 unsigned blockSizeInWords,
00900 UINT32 rawIdleBlockPattern,
00901 IxHssAccPktHdlcFraming hdlcTxFraming,
00902 IxHssAccPktHdlcFraming hdlcRxFraming,
00903 unsigned frmFlagStart,
00904 IxHssAccPktRxCallback rxCallback,
00905 IxHssAccPktUserId rxUserId,
00906 IxHssAccPktRxFreeLowCallback rxFreeLowCallback,
00907 IxHssAccPktUserId rxFreeLowUserId,
00908 IxHssAccPktTxDoneCallback txDoneCallback,
00909 IxHssAccPktUserId txDoneUserId);
00910
00938 PUBLIC IX_STATUS
00939 ixHssAccPktPortEnable (IxHssAccHssPort hssPortId,
00940 IxHssAccHdlcPort hdlcPortId);
00941
00963 PUBLIC IX_STATUS
00964 ixHssAccPktPortDisable (IxHssAccHssPort hssPortId,
00965 IxHssAccHdlcPort hdlcPortId);
00966
00992 PUBLIC IX_STATUS
00993 ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId,
00994 IxHssAccHdlcPort hdlcPortId);
00995
01019 PUBLIC BOOL
01020 ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId,
01021 IxHssAccHdlcPort hdlcPortId);
01022
01023
01053 PUBLIC IX_STATUS
01054 ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId,
01055 IxHssAccHdlcPort hdlcPortId,
01056 IX_MBUF *buffer);
01057
01099 PUBLIC IX_STATUS
01100 ixHssAccPktPortTx (IxHssAccHssPort hssPortId,
01101 IxHssAccHdlcPort hdlcPortId,
01102 IX_MBUF *buffer);
01103
01163 PUBLIC IX_STATUS
01164 ixHssAccChanConnect (IxHssAccHssPort hssPortId,
01165 unsigned bytesPerTSTrigger,
01166 UINT8 *rxCircular,
01167 unsigned numRxBytesPerTS,
01168 UINT32 *txPtrList,
01169 unsigned numTxPtrLists,
01170 unsigned numTxBytesPerBlk,
01171 IxHssAccChanRxCallback rxCallback);
01172
01194 PUBLIC IX_STATUS
01195 ixHssAccChanPortEnable (IxHssAccHssPort hssPortId);
01196
01219 PUBLIC IX_STATUS
01220 ixHssAccChanPortDisable (IxHssAccHssPort hssPortId);
01221
01243 PUBLIC IX_STATUS
01244 ixHssAccChanDisconnect (IxHssAccHssPort hssPortId);
01245
01283 PUBLIC IX_STATUS
01284 ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId,
01285 BOOL *dataRecvd,
01286 unsigned *rxOffset,
01287 unsigned *txOffset,
01288 unsigned *numHssErrs);
01289
01301 PUBLIC void
01302 ixHssAccShow (void);
01303
01314 PUBLIC void
01315 ixHssAccStatsInit (void);
01316
01317 #endif
01318