00001
00052 #ifndef IxEthAcc_H
00053 #define IxEthAcc_H
00054
00055 #include <IxOsBuffMgt.h>
00056 #include <IxTypes.h>
00057
00071 typedef enum
00072 {
00073 IX_ETH_ACC_SUCCESS = IX_SUCCESS,
00074 IX_ETH_ACC_FAIL = IX_FAIL,
00075 IX_ETH_ACC_INVALID_PORT,
00076 IX_ETH_ACC_PORT_UNINITIALIZED,
00077 IX_ETH_ACC_MAC_UNINITIALIZED,
00078 IX_ETH_ACC_INVALID_ARG,
00079 IX_ETH_TX_Q_FULL,
00080 IX_ETH_ACC_NO_SUCH_ADDR
00081 } IxEthAccStatus;
00082
00088 typedef enum
00089 {
00090 IX_ETH_PORT_1 = 0,
00091 IX_ETH_PORT_2 = 1
00092 } IxEthAccPortId;
00093
00102 #define IX_ETH_ACC_NUMBER_OF_PORTS (2)
00103
00112 #define IX_IEEE803_MAC_ADDRESS_SIZE (6)
00113
00122 typedef struct
00123 {
00124 UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE];
00125 } IxEthAccMacAddr;
00126
00133 #define IX_ETH_ACC_NUM_TX_PRIORITIES (8)
00134
00141 typedef enum
00142 {
00143 IX_ETH_ACC_TX_PRIORITY_0 = 0,
00144 IX_ETH_ACC_TX_PRIORITY_1 = 1,
00145 IX_ETH_ACC_TX_PRIORITY_2 = 2,
00146 IX_ETH_ACC_TX_PRIORITY_3 = 3,
00147 IX_ETH_ACC_TX_PRIORITY_4 = 4,
00148 IX_ETH_ACC_TX_PRIORITY_5 = 5,
00149 IX_ETH_ACC_TX_PRIORITY_6 = 6,
00150 IX_ETH_ACC_TX_PRIORITY_7 = 7,
00152 IX_ETH_ACC_TX_DEFAULT_PRIORITY = IX_ETH_ACC_TX_PRIORITY_0
00154 } IxEthAccTxPriority;
00155
00162 typedef enum
00163 {
00164 IX_ETH_ACC_FULL_DUPLEX,
00165 IX_ETH_ACC_HALF_DUPLEX
00166 } IxEthAccDuplexMode;
00167
00168
00176 #define IX_ETHACC_RX_MBUF_MIN_SIZE (2048)
00177
00186 #define IXP425_ETH_ACC_MII_MAX_ADDR 32
00187
00211 IxEthAccStatus ixEthAccInit(void);
00212
00213
00228 void ixEthAccUnload(void);
00229
00266 IxEthAccStatus ixEthAccPortInit(IxEthAccPortId portId);
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00280
00330 IxEthAccStatus ixEthAccPortTxFrameSubmit(
00331 IxEthAccPortId portId,
00332 IX_MBUF *buffer,
00333 IxEthAccTxPriority priority
00334 );
00335
00368 typedef void (*IxEthAccPortTxDoneCallback) ( UINT32 callbackTag, IX_MBUF *buffer );
00369
00370
00371
00409 IxEthAccStatus ixEthAccPortTxDoneCallbackRegister( IxEthAccPortId portId,
00410 IxEthAccPortTxDoneCallback txCallbackFn,
00411 UINT32 callbackTag);
00412
00413
00414
00473 typedef void (*IxEthAccPortRxCallback) (UINT32 callbackTag, IX_MBUF *buffer, IxEthAccPortId portId);
00474
00475
00476
00477
00510 IxEthAccStatus ixEthAccPortRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortRxCallback rxCallbackFn, UINT32 callbackTag);
00511
00512
00575 IxEthAccStatus ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_MBUF *buffer);
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00627 IxEthAccStatus ixEthAccPortEnable(IxEthAccPortId portId);
00628
00655 IxEthAccStatus ixEthAccPortDisable(IxEthAccPortId portId);
00656
00680 IxEthAccStatus ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled);
00681
00728 IxEthAccStatus ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId);
00729
00730
00774 IxEthAccStatus ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId);
00775
00798 IxEthAccStatus ixEthAccPortUnicastMacAddressSet( IxEthAccPortId portId,
00799 IxEthAccMacAddr *macAddr);
00800
00828 IxEthAccStatus ixEthAccPortUnicastMacAddressGet( IxEthAccPortId portId,
00829 IxEthAccMacAddr *macAddr);
00830
00831
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00884 IxEthAccStatus ixEthAccPortMulticastAddressJoin( IxEthAccPortId portId,
00885 IxEthAccMacAddr *macAddr);
00886
00932 IxEthAccStatus ixEthAccPortMulticastAddressJoinAll( IxEthAccPortId portId);
00933
00977 IxEthAccStatus ixEthAccPortMulticastAddressLeave( IxEthAccPortId portId,
00978 IxEthAccMacAddr *macAddr);
00979
01021 IxEthAccStatus ixEthAccPortMulticastAddressLeaveAll( IxEthAccPortId portId);
01022
01062 IxEthAccStatus ixEthAccPortUnicastAddressShow(IxEthAccPortId portId);
01063
01064
01082 void ixEthAccPortMulticastAddressShow( IxEthAccPortId portId);
01083
01109 IxEthAccStatus ixEthAccPortDuplexModeSet( IxEthAccPortId portId, IxEthAccDuplexMode mode );
01110
01138 IxEthAccStatus ixEthAccPortDuplexModeGet( IxEthAccPortId portId, IxEthAccDuplexMode *mode );
01139
01140
01141
01142
01143
01173 IxEthAccStatus ixEthAccPortTxFrameAppendPaddingEnable( IxEthAccPortId portId);
01174
01200 IxEthAccStatus ixEthAccPortTxFrameAppendPaddingDisable( IxEthAccPortId portId);
01201
01225 IxEthAccStatus ixEthAccPortTxFrameAppendFCSEnable( IxEthAccPortId portId);
01226
01257 IxEthAccStatus ixEthAccPortTxFrameAppendFCSDisable( IxEthAccPortId portId);
01258
01283 IxEthAccStatus ixEthAccPortRxFrameAppendFCSEnable( IxEthAccPortId portId);
01284
01310 IxEthAccStatus ixEthAccPortRxFrameAppendFCSDisable( IxEthAccPortId portId);
01311
01312
01313
01314
01333 typedef enum
01334 {
01335 FIFO_NO_PRIORITY,
01336 FIFO_PRIORITY
01337 }IxEthAccTxSchedulerDiscipline;
01338
01339
01367 IxEthAccStatus ixEthAccTxSchedulingDisciplineSet( IxEthAccPortId portId, IxEthAccTxSchedulerDiscipline sched);
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01389 typedef struct
01390 {
01391 UINT32 dot3StatsAlignmentErrors;
01392 UINT32 dot3StatsFCSErrors;
01393 UINT32 dot3StatsFrameTooLongs;
01394 UINT32 dot3StatsInternalMacReceiveErrors;
01395 UINT32 LearnedEntryDiscards;
01396 UINT32 UnderflowEntryDiscards;
01397 UINT32 dot3StatsSingleCollisionFrames;
01398 UINT32 dot3StatsMultipleCollisionFrames;
01399 UINT32 dot3StatsDeferredTransmissions;
01400 UINT32 dot3StatsLateCollisions;
01401 UINT32 dot3StatsExcessiveCollsions;
01402 UINT32 dot3StatsInternalMacTransmitErrors;
01403 UINT32 dot3StatsCarrierSenseErrors;
01404 }IxEthEthObjStats;
01405
01435 IxEthAccStatus ixEthAccMibIIStatsGet(IxEthAccPortId portId ,IxEthEthObjStats *retStats );
01436
01465 IxEthAccStatus ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats);
01466
01492 IxEthAccStatus ixEthAccMibIIStatsClear(IxEthAccPortId portId);
01493
01512 IxEthAccStatus ixEthAccMacInit(IxEthAccPortId portId);
01513
01535 void ixEthAccStatsShow(IxEthAccPortId portId);
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01578 IxEthAccStatus ixEthAccMiiReadRtn (UINT8 phyAddr,
01579 UINT8 phyReg,
01580 UINT16 *value);
01581
01611 IxEthAccStatus ixEthAccMiiWriteRtn (UINT8 phyAddr,
01612 UINT8 phyReg,
01613 UINT16 value);
01614
01639 IxEthAccStatus ixEthAccMiiStatsShow (UINT32 phyAddr);
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01650
01651 #include "IxEthMii.h"
01652
01666 #define ixEthAccMiiPhyScan(phyPresent) ixEthMiiPhyScan(phyPresent,IXP425_ETH_ACC_MII_MAX_ADDR)
01667
01680 #define ixEthAccMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate) \
01681 ixEthMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate)
01682
01695 #define ixEthAccMiiPhyReset(phyAddr) \
01696 ixEthMiiPhyReset(phyAddr)
01697
01710 #define ixEthAccMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg) \
01711 ixEthMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg)
01712
01713
01714
01727 #define ixEthAccMiiShow(phyAddr) \
01728 ixEthMiiPhyShow(phyAddr)
01729
01730 #endif
01731