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IxOsServicesMemAccess.h

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00001 
00048 #ifndef IxOsServicesMemAccess_H
00049 #define IxOsServicesMemAccess_H
00050 
00051 #include "IxTypes.h"
00052 #include "IxOsServicesEndianess.h"
00053 
00138 /* Global BE switch
00139  * 
00140  *  Should be set only in BE mode and only if the component uses I/O memory.
00141  *  If I/O memory is not used the component-specific section in IxOsServicesComponents.h
00142  *  should #define CSR_NO_MAPPING instead */
00143 #if defined (__BIG_ENDIAN)
00144 
00145 #define CSR_BE_MAPPING
00146 
00147 #endif /* Global BE switch */
00148 
00149 /* By default only static memory maps in use;
00150    define IX_DYNAMIC_MEMORY_MAP per component if dynamic maps are
00151    used instead in that component */
00152 #define IX_STATIC_MEMORY_MAP
00153 
00154 /* SDRAM coherency mode
00155 
00156    Must be defined to BE, LE_DATA_COHERENT or LE_ADDRESS_COHERENT.
00157    The mode changes depending on OS */
00158 #if defined (IX_OSSERV_LINUX_BE) || defined (IX_OSSERV_VXWORKS_BE)
00159 
00160 #define IX_SDRAM_BE
00161 
00162 #elif defined (IX_OSSERV_VXWORKS_LE)
00163 
00164 #define IX_SDRAM_LE_DATA_COHERENT
00165 
00166 #endif
00167   
00168 /**************************************
00169  * Retrieve current component mapping *
00170  **************************************/
00171 
00172 #include <IxOsServicesComponents.h>
00173 
00174 /*******************************************************************
00175  * Turn off IX_STATIC_MEMORY map for components using dynamic maps *
00176  *******************************************************************/
00177 #ifdef IX_DYNAMIC_MEMORY_MAP
00178 
00179 #undef IX_STATIC_MEMORY_MAP
00180 
00181 #endif
00182 
00183 /************************************************************
00184  * Turn off BE access for components using LE or no mapping *
00185  ************************************************************/
00186 #if (defined (CSR_LE_ADDRESS_COHERENT_MAPPING) || defined (CSR_LE_DATA_COHERENT_MAPPING) || defined (CSR_NO_MAPPING)) \
00187      && defined (CSR_BE_MAPPING)
00188 
00189 #undef CSR_BE_MAPPING
00190 
00191 #endif
00192 
00193 /*****************
00194  * Safety checks *
00195  *****************/
00196 
00197 /* At least one mapping must be defined - BE, LE_AC, LE_DC or NO_MAPPING */
00198 #if !defined (CSR_BE_MAPPING) && !defined (CSR_LE_ADDRESS_COHERENT_MAPPING) && !defined (CSR_LE_DATA_COHERENT_MAPPING) && !defined (CSR_NO_MAPPING)
00199 
00200 #error No I/O mapping is defined, unsupported component
00201 
00202 #endif /* check at least one mapping */
00203 
00204 /* No more than one mapping can be defined for a component */
00205 #if (defined (CSR_BE_MAPPING) && (defined (CSR_LE_ADDRESS_COHERENT_MAPPING) || defined (CSR_LE_DATA_COHERENT_MAPPING) || defined (CSR_NO_MAPPING))) \
00206     || (defined (CSR_LE_ADDRESS_COHERENT_MAPPING) && (defined (CSR_BE_MAPPING) || defined (CSR_LE_DATA_COHERENT_MAPPING) || defined (CSR_NO_MAPPING))) \
00207     || (defined (CSR_LE_DATA_COHERENT_MAPPING) && (defined (CSR_BE_MAPPING) || defined (CSR_LE_ADDRESS_COHERENT_MAPPING) || defined (CSR_NO_MAPPING))) \
00208     || (defined (CSR_NO_MAPPING) && (defined (CSR_BE_MAPPING) || defined (CSR_LE_ADDRESS_COHERENT_MAPPING) || defined (CSR_LE_DATA_COHERENT_MAPPING)))
00209     
00210 #ifdef CSR_BE_MAPPING
00211 #warning CSR_BE_MAPPING is defined
00212 #endif
00213 
00214 #ifdef CSR_LE_ADDRESS_COHERENT_MAPPING
00215 #warning CSR_LE_ADDRESS_COHERENT_MAPPING is defined
00216 #endif
00217 
00218 #ifdef CSR_LE_DATA_COHERENT_MAPPING
00219 #warning CSR_LE_DATA_COHERENT_MAPPING is defined
00220 #endif
00221     
00222 #error More than one I/O mapping is defined, please check your component mapping
00223 
00224 #endif /* check at most one mapping */
00225 
00226 /* SDRAM coherency should be defined */
00227 #if !defined (IX_SDRAM_BE) && !defined (IX_SDRAM_LE_DATA_COHERENT) && !defined (IX_SDRAM_LE_ADDRESS_COHERENT)
00228 
00229 #error SDRAM coherency must be defined
00230 
00231 #endif /* SDRAM coherency must be defined */
00232 
00233 /* SDRAM coherency cannot be defined in several ways */
00234 #if (defined (IX_SDRAM_BE) && (defined (IX_SDRAM_LE_DATA_COHERENT) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
00235     || (defined (IX_SDRAM_LE_DATA_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_ADDRESS_COHERENT))) \
00236     || (defined (IX_SDRAM_LE_ADDRESS_COHERENT) && (defined (IX_SDRAM_BE) || defined (IX_SDRAM_LE_DATA_COHERENT)))
00237 
00238 #error SDRAM coherency cannot be defined in more than one way
00239 
00240 #endif /* SDRAM coherency must be defined exactly once */
00241   
00242 /*********************
00243  * Read/write macros *
00244  *********************/
00245 
00246 /* WARNING - except for addition of special cookie read/write macros (see below)
00247              these macros are NOT user serviceable. Please do not modify */
00248 
00249 #define IX_OSSERV_READ_LONG_RAW(wAddr)          (*(wAddr))
00250 #define IX_OSSERV_READ_SHORT_RAW(sAddr)         (*(sAddr))
00251 #define IX_OSSERV_READ_BYTE_RAW(bAddr)          (*(bAddr))
00252 #define IX_OSSERV_WRITE_LONG_RAW(wAddr, wData)  (*(wAddr) = (wData))
00253 #define IX_OSSERV_WRITE_SHORT_RAW(sAddr,sData)  (*(sAddr) = (sData))
00254 #define IX_OSSERV_WRITE_BYTE_RAW(bAddr, bData)  (*(bAddr) = (bData))
00255 
00256 #ifdef __linux
00257 
00258 /* Linux - specific cookie reads/writes. 
00259   Redefine per OS if dynamic memory maps are used
00260   and I/O memory is accessed via functions instead of raw pointer access. */
00261   
00262 #define IX_OSSERV_READ_LONG_COOKIE(wCookie)           (readl((UINT32)wCookie))
00263 #define IX_OSSERV_READ_SHORT_COOKIE(sCookie)          (readw((UINT32)sCookie))
00264 #define IX_OSSERV_READ_BYTE_COOKIE(bCookie)           (readb((UINT32)bCookie))
00265 #define IX_OSSERV_WRITE_LONG_COOKIE(wCookie, wData)   (writel(wData, (UINT32)wCookie))
00266 #define IX_OSSERV_WRITE_SHORT_COOKIE(sCookie, sData)  (writew(sData, (UINT32)sCookie))
00267 #define IX_OSSERV_WRITE_BYTE_COOKIE(bCookie, bData)   (writeb(bData, (UINT32)bCookie))
00268 
00269 #endif /* linux */
00270 
00271 #if defined (__vxworks) || (defined (__linux) && defined (IX_STATIC_MEMORY_MAP))
00272 
00273 #define IX_OSSERV_READ_LONG_IO(wAddr)            IX_OSSERV_READ_LONG_RAW(wAddr)
00274 #define IX_OSSERV_READ_SHORT_IO(sAddr)           IX_OSSERV_READ_SHORT_RAW(sAddr)
00275 #define IX_OSSERV_READ_BYTE_IO(bAddr)            IX_OSSERV_READ_BYTE_RAW(bAddr)
00276 #define IX_OSSERV_WRITE_LONG_IO(wAddr, wData)    IX_OSSERV_WRITE_LONG_RAW(wAddr, wData)
00277 #define IX_OSSERV_WRITE_SHORT_IO(sAddr, sData)   IX_OSSERV_WRITE_SHORT_RAW(sAddr, sData)
00278 #define IX_OSSERV_WRITE_BYTE_IO(bAddr, bData)    IX_OSSERV_WRITE_BYTE_RAW(bAddr, bData)
00279 
00280 #elif defined (__linux) && !defined (IX_STATIC_MEMORY_MAP)
00281 
00282 #include <asm/io.h>
00283 
00284 #define IX_OSSERV_READ_LONG_IO(wAddr)            IX_OSSERV_READ_LONG_COOKIE(wAddr)
00285 #define IX_OSSERV_READ_SHORT_IO(sAddr)           IX_OSSERV_READ_SHORT_COOKIE(sAddr)
00286 #define IX_OSSERV_READ_BYTE_IO(bAddr)            IX_OSSERV_READ_BYTE_COOKIE(bAddr)
00287 #define IX_OSSERV_WRITE_LONG_IO(wAddr, wData)    IX_OSSERV_WRITE_LONG_COOKIE(wAddr, wData)
00288 #define IX_OSSERV_WRITE_SHORT_IO(sAddr, sData)   IX_OSSERV_WRITE_SHORT_COOKIE(sAddr, sData)
00289 #define IX_OSSERV_WRITE_BYTE_IO(bAddr, bData)    IX_OSSERV_WRITE_BYTE_COOKIE(bAddr, bData)
00290 
00291 #endif
00292 
00293 #if defined (CSR_BE_MAPPING)
00294 
00295 #define IX_OSSERV_READ_LONG(wAddr)          IX_OSSERV_BE_BUSTOXSL(IX_OSSERV_READ_LONG_IO((volatile UINT32 *) wAddr))
00296 #define IX_OSSERV_READ_SHORT(sAddr)         IX_OSSERV_BE_BUSTOXSS(IX_OSSERV_READ_SHORT_IO((volatile UINT16 *) sAddr))
00297 #define IX_OSSERV_READ_BYTE(bAddr)          IX_OSSERV_BE_BUSTOXSB(IX_OSSERV_READ_BYTE_IO((volatile UINT8 *) bAddr))
00298 #define IX_OSSERV_WRITE_LONG(wAddr, wData)  IX_OSSERV_WRITE_LONG_IO((volatile UINT32 *) wAddr, IX_OSSERV_BE_XSTOBUSL((UINT32) wData))
00299 #define IX_OSSERV_WRITE_SHORT(sAddr, sData) IX_OSSERV_WRITE_SHORT_IO((volatile UINT16 *) sAddr, IX_OSSERV_BE_XSTOBUSS((UINT16) sData))
00300 #define IX_OSSERV_WRITE_BYTE(bAddr, bData)  IX_OSSERV_WRITE_BYTE_IO((volatile UINT8 *) bAddr, IX_OSSERV_BE_XSTOBUSB((UINT8) bData))
00301 
00302 #elif defined (CSR_LE_ADDRESS_COHERENT_MAPPING)
00303 
00304 #define IX_OSSERV_READ_LONG(wAddr)          IX_OSSERV_READ_LONG_IO((volatile UINT32 *) IX_OSSERV_LE_AC_BUSTOXSL((UINT32) wAddr))
00305 #define IX_OSSERV_READ_SHORT(sAddr)         IX_OSSERV_READ_SHORT_IO((volatile UINT16 *) IX_OSSERV_LE_AC_BUSTOXSS((UINT32) sAddr))
00306 #define IX_OSSERV_READ_BYTE(bAddr)          IX_OSSERV_READ_BYTE_IO((volatile UINT8 *) IX_OSSERV_LE_AC_BUSTOXSB((UINT32) bAddr))
00307 #define IX_OSSERV_WRITE_LONG(wAddr, wData)  IX_OSSERV_WRITE_LONG_IO((volatile UINT32 *) IX_OSSERV_LE_AC_XSTOBUSL((UINT32) wAddr), (UINT32) wData)
00308 #define IX_OSSERV_WRITE_SHORT(sAddr, sData) IX_OSSERV_WRITE_SHORT_IO((volatile UINT16 *) IX_OSSERV_LE_AC_XSTOBUSS((UINT32) sAddr), (UINT16) sData)
00309 #define IX_OSSERV_WRITE_BYTE(bAddr, bData)  IX_OSSERV_WRITE_BYTE_IO((volatile UINT8 *) IX_OSSERV_LE_AC_XSTOBUSB((UINT32) bAddr), (UINT8) bData)
00310 
00311 #elif defined (CSR_LE_DATA_COHERENT_MAPPING)
00312 
00313 /* Inline functions are required here to avoid reading the same I/O location 2 or 4 times for the byte swap */
00314 static __inline__ UINT32 ixOsServDataCoherentLongReadSwap(volatile UINT32 *wAddr)
00315 {
00316   UINT32 wData = IX_OSSERV_READ_LONG_IO(wAddr);
00317   return IX_OSSERV_LE_DC_BUSTOXSL(wData);
00318 }
00319 
00320 static __inline__ UINT16 ixOsServDataCoherentShortReadSwap(volatile UINT16 *sAddr)
00321 {
00322   UINT16 sData = IX_OSSERV_READ_SHORT_IO(sAddr);
00323   return IX_OSSERV_LE_DC_BUSTOXSS(sData);
00324 }
00325 
00326 static __inline__ void ixOsServDataCoherentLongWriteSwap(volatile UINT32 *wAddr, UINT32 wData)
00327 {
00328   wData = IX_OSSERV_LE_DC_XSTOBUSL(wData);
00329   IX_OSSERV_WRITE_LONG_IO(wAddr, wData);
00330 }
00331 
00332 static __inline__ void ixOsServDataCoherentShortWriteSwap(volatile UINT16 *sAddr, UINT16 sData)
00333 {
00334   sData = IX_OSSERV_LE_DC_XSTOBUSS(sData);
00335   IX_OSSERV_WRITE_LONG_IO(sAddr, sData);
00336 }
00337 
00338 #define IX_OSSERV_READ_LONG(wAddr)          ixOsServDataCoherentLongReadSwap((volatile UINT32 *) wAddr)
00339 #define IX_OSSERV_READ_SHORT(sAddr)         ixOsServDataCoherentShortReadSwap((volatile UINT16 *) sAddr)
00340 #define IX_OSSERV_READ_BYTE(bAddr)          IX_OSSERV_LE_DC_BUSTOXSB(IX_OSSERV_READ_BYTE_IO((volatile UINT8 *) bAddr))
00341 #define IX_OSSERV_WRITE_LONG(wAddr, wData)  ixOsServDataCoherentLongWriteSwap((volatile UINT32 *) wAddr, (UINT32) wData)
00342 #define IX_OSSERV_WRITE_SHORT(sAddr, sData) ixOsServDataCoherentShortWriteSwap((volatile UINT16 *) sAddr, (UINT16) sData)
00343 #define IX_OSSERV_WRITE_BYTE(bAddr, bData)  IX_OSSERV_WRITE_BYTE_IO((volatile UINT8 *) bAddr, IX_OSSERV_LE_DC_XSTOBUSB((UINT8) bData))
00344 
00345 #endif
00346 
00347 /* Reads/writes to and from memory shared with NPEs - depends on the SDRAM coherency */
00348 #if defined (IX_SDRAM_BE)
00349 
00350 #define IX_OSSERV_READ_NPE_SHARED_LONG(wAddr)            IX_OSSERV_READ_LONG_RAW(wAddr)
00351 #define IX_OSSERV_READ_NPE_SHARED_SHORT(sAddr)           IX_OSSERV_READ_SHORT_RAW(sAddr)
00352 #define IX_OSSERV_WRITE_NPE_SHARED_LONG(wAddr, wData)    IX_OSSERV_WRITE_LONG_RAW(wAddr, wData)
00353 #define IX_OSSERV_WRITE_NPE_SHARED_SHORT(sAddr, sData)   IX_OSSERV_WRITE_SHORT_RAW(sAddr, sData)
00354 
00355 #define IX_OSSERV_SWAP_NPE_SHARED_LONG(wData)            (wData)
00356 #define IX_OSSERV_SWAP_NPE_SHARED_SHORT(sData)           (sData)
00357 
00358 #elif defined (IX_SDRAM_LE_ADDRESS_COHERENT)
00359 
00360 #define IX_OSSERV_READ_NPE_SHARED_LONG(wAddr)            IX_OSSERV_READ_LONG_RAW(wAddr)
00361 #define IX_OSSERV_READ_NPE_SHARED_SHORT(sAddr)           IX_OSSERV_READ_SHORT_RAW(IX_OSSERV_SWAP_SHORT_ADDRESS(sAddr))
00362 #define IX_OSSERV_WRITE_NPE_SHARED_LONG(wAddr, wData)    IX_OSSERV_WRITE_LONG_RAW(wAddr, wData)
00363 #define IX_OSSERV_WRITE_NPE_SHARED_SHORT(sAddr, sData)   IX_OSSERV_WRITE_SHORT_RAW(IX_OSSERV_SWAP_SHORT_ADDRESS(sAddr), sData)
00364 
00365 #define IX_OSSERV_SWAP_NPE_SHARED_LONG(wData)            (wData)
00366 #define IX_OSSERV_SWAP_NPE_SHARED_SHORT(sData)           (sData)
00367 
00368 #elif defined (IX_SDRAM_LE_DATA_COHERENT)
00369 
00370 #define IX_OSSERV_READ_NPE_SHARED_LONG(wAddr)            IX_OSSERV_SWAP_LONG(IX_OSSERV_READ_LONG_RAW(wAddr))
00371 #define IX_OSSERV_READ_NPE_SHARED_SHORT(sAddr)           IX_OSSERV_SWAP_SHORT(IX_OSSERV_READ_SHORT_RAW(sAddr))
00372 #define IX_OSSERV_WRITE_NPE_SHARED_LONG(wAddr, wData)    IX_OSSERV_WRITE_LONG_RAW(wAddr, IX_OSSERV_SWAP_LONG(wData))
00373 #define IX_OSSERV_WRITE_NPE_SHARED_SHORT(sAddr, sData)   IX_OSSERV_WRITE_SHORT_RAW(sAddr, IX_OSSERV_SWAP_SHORT(sData))
00374 
00375 #define IX_OSSERV_SWAP_NPE_SHARED_LONG(wData)            IX_OSSERV_SWAP_LONG(wData)
00376 #define IX_OSSERV_SWAP_NPE_SHARED_SHORT(sData)           IX_OSSERV_SWAP_SHORT(sData)
00377 
00378 #endif
00379 
00380 #define IX_OSSERV_COPY_NPE_SHARED_LONG_ARRAY(wDestAddr, wSrcAddr, wCount) \
00381   { \
00382     UINT32 i; \
00383     \
00384     for ( i = 0 ; i < wCount ; i++ ) \
00385     { \
00386       * ((UINT32 *) wDestAddr) + i) = IX_OSSERV_READ_SHARED_NPE_LONG(((UINT32 *) wSrcAddr) + i); \
00387     }; \
00388   };
00389 
00390 #endif /* IxOsServicesMemAccess_H */
Automatically generated from sources. © Intel Corp. 2003