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IxQMgr.h

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00001 
00064 /* ------------------------------------------------------
00065    Doxygen group definitions
00066    ------------------------------------------------------ */
00077 #ifndef IXQMGR_H
00078 #define IXQMGR_H
00079 
00080 /*
00081  * User defined include files
00082  */
00083 #include "IxTypes.h"
00084 
00093 #define IX_QMGR_SAVED_COMPONENT_NAME IX_COMPONENT_NAME
00094 #undef  IX_COMPONENT_NAME
00095 #define IX_COMPONENT_NAME ix_qmgr
00096 #include "IxOsServicesMemAccess.h"
00097 
00098 
00099 /*
00100  * #defines and macros
00101  */
00102 
00115 #ifdef IXQMGRQACCESS_C
00116 /* If IXQMGRQACCESS_C is set then the IxQmgrQAccess.c is including this file
00117    and must instantiate a concrete definition for each inlineable API function
00118    whether or not that function actually gets inlined. */
00119 #    ifdef NO_INLINE_APIS
00120 #        undef NO_INLINE_APIS
00121 #    endif
00122 #    define IX_QMGR_INLINE  /* Empty Define */
00123 #else
00124 #    ifndef NO_INLINE_APIS
00125 #       define IX_QMGR_INLINE __inline__ extern
00126 #    else
00127 #       define IX_QMGR_INLINE /* Empty Define */
00128 #    endif
00129 #endif
00130 
00142 #define IX_QMGR_MAX_NUM_QUEUES  64
00143 
00155 #define IX_QMGR_MIN_QID IX_QMGR_QUEUE_0
00156 
00168 #define IX_QMGR_MAX_QID IX_QMGR_QUEUE_63
00169 
00182 #define IX_QMGR_MIN_QUEUPP_QID 32
00183 
00196 #define IX_QMGR_MAX_QNAME_LEN 16
00197 
00209 #define IX_QMGR_WARNING 2
00210 
00222 #define IX_QMGR_PARAMETER_ERROR 3
00223 
00235 #define IX_QMGR_INVALID_Q_ENTRY_SIZE 4
00236 
00248 #define IX_QMGR_INVALID_Q_ID 5
00249 
00260 #define IX_QMGR_INVALID_CB_ID 6
00261 
00273 #define IX_QMGR_CB_ALREADY_SET 7
00274 
00286 #define IX_QMGR_NO_AVAILABLE_SRAM 8
00287 
00298 #define IX_QMGR_INVALID_INT_SOURCE_ID 9
00299 
00312 #define IX_QMGR_INVALID_QSIZE 10
00313 
00324 #define IX_QMGR_INVALID_Q_WM 11
00325 
00338 #define IX_QMGR_Q_NOT_CONFIGURED 12
00339 
00350 #define IX_QMGR_Q_ALREADY_CONFIGURED 13
00351 
00363 #define IX_QMGR_Q_UNDERFLOW 14
00364 
00376 #define IX_QMGR_Q_OVERFLOW 15
00377 
00388 #define IX_QMGR_Q_INVALID_PRIORITY 16
00389 
00400 #define IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS 17
00401 
00412 #define ixQMgrDispatcherLoopRun ixQMgrDispatcherLoopRunA0
00413 
00414 /*
00415  * Typedefs
00416  */
00417 
00433 typedef enum
00434 {
00435     IX_QMGR_QUEUE_0 = 0,
00436     IX_QMGR_QUEUE_1,
00437     IX_QMGR_QUEUE_2,
00438     IX_QMGR_QUEUE_3,
00439     IX_QMGR_QUEUE_4,
00440     IX_QMGR_QUEUE_5,
00441     IX_QMGR_QUEUE_6,
00442     IX_QMGR_QUEUE_7,
00443     IX_QMGR_QUEUE_8,
00444     IX_QMGR_QUEUE_9,
00445     IX_QMGR_QUEUE_10,
00446     IX_QMGR_QUEUE_11,
00447     IX_QMGR_QUEUE_12,
00448     IX_QMGR_QUEUE_13,
00449     IX_QMGR_QUEUE_14,
00450     IX_QMGR_QUEUE_15,
00451     IX_QMGR_QUEUE_16,
00452     IX_QMGR_QUEUE_17,
00453     IX_QMGR_QUEUE_18,
00454     IX_QMGR_QUEUE_19,
00455     IX_QMGR_QUEUE_20,
00456     IX_QMGR_QUEUE_21,
00457     IX_QMGR_QUEUE_22,
00458     IX_QMGR_QUEUE_23,
00459     IX_QMGR_QUEUE_24,
00460     IX_QMGR_QUEUE_25,
00461     IX_QMGR_QUEUE_26,
00462     IX_QMGR_QUEUE_27,
00463     IX_QMGR_QUEUE_28,
00464     IX_QMGR_QUEUE_29,
00465     IX_QMGR_QUEUE_30,
00466     IX_QMGR_QUEUE_31,
00467     IX_QMGR_QUEUE_32,
00468     IX_QMGR_QUEUE_33,
00469     IX_QMGR_QUEUE_34,
00470     IX_QMGR_QUEUE_35,
00471     IX_QMGR_QUEUE_36,
00472     IX_QMGR_QUEUE_37,
00473     IX_QMGR_QUEUE_38,
00474     IX_QMGR_QUEUE_39,
00475     IX_QMGR_QUEUE_40,
00476     IX_QMGR_QUEUE_41,
00477     IX_QMGR_QUEUE_42,
00478     IX_QMGR_QUEUE_43,
00479     IX_QMGR_QUEUE_44,
00480     IX_QMGR_QUEUE_45,
00481     IX_QMGR_QUEUE_46,
00482     IX_QMGR_QUEUE_47,
00483     IX_QMGR_QUEUE_48,
00484     IX_QMGR_QUEUE_49,
00485     IX_QMGR_QUEUE_50,
00486     IX_QMGR_QUEUE_51,
00487     IX_QMGR_QUEUE_52,
00488     IX_QMGR_QUEUE_53,
00489     IX_QMGR_QUEUE_54,
00490     IX_QMGR_QUEUE_55,
00491     IX_QMGR_QUEUE_56,
00492     IX_QMGR_QUEUE_57,
00493     IX_QMGR_QUEUE_58,
00494     IX_QMGR_QUEUE_59,
00495     IX_QMGR_QUEUE_60,
00496     IX_QMGR_QUEUE_61,
00497     IX_QMGR_QUEUE_62,
00498     IX_QMGR_QUEUE_63,
00499     IX_QMGR_QUEUE_INVALID
00500 } IxQMgrQId;
00501 
00523 typedef UINT32 IxQMgrQStatus;
00524 
00536 typedef enum
00537 {
00538     IX_QMGR_Q_STATUS_E_BIT_MASK  = 0x1,
00539     IX_QMGR_Q_STATUS_NE_BIT_MASK = 0x2,
00540     IX_QMGR_Q_STATUS_NF_BIT_MASK = 0x4,
00541     IX_QMGR_Q_STATUS_F_BIT_MASK  = 0x8,
00542     IX_QMGR_Q_STATUS_UF_BIT_MASK = 0x10,
00543     IX_QMGR_Q_STATUS_OF_BIT_MASK = 0x20
00544 } IxQMgrQStatusMask;
00545 
00559 typedef enum
00560 {
00561     IX_QMGR_Q_SOURCE_ID_E = 0,  
00562     IX_QMGR_Q_SOURCE_ID_NE,     
00563     IX_QMGR_Q_SOURCE_ID_NF,     
00564     IX_QMGR_Q_SOURCE_ID_F,      
00565     IX_QMGR_Q_SOURCE_ID_NOT_E,  
00566     IX_QMGR_Q_SOURCE_ID_NOT_NE, 
00567     IX_QMGR_Q_SOURCE_ID_NOT_NF, 
00568     IX_QMGR_Q_SOURCE_ID_NOT_F   
00569 } IxQMgrSourceId;
00570 
00581 typedef enum
00582 {
00583     IX_QMGR_Q_ENTRY_SIZE1 = 1,   
00584     IX_QMGR_Q_ENTRY_SIZE2 = 2,   
00585     IX_QMGR_Q_ENTRY_SIZE4 = 4    
00586 } IxQMgrQEntrySizeInWords;
00587 
00599 typedef enum
00600 {
00601     IX_QMGR_Q_SIZE16 = 16,   
00602     IX_QMGR_Q_SIZE32 = 32,   
00603     IX_QMGR_Q_SIZE64 = 64,   
00604     IX_QMGR_Q_SIZE128 = 128, 
00605     IX_QMGR_Q_SIZE_INVALID = 129  
00608 } IxQMgrQSizeInWords;
00609 
00627 typedef enum
00628 {
00629     IX_QMGR_Q_WM_LEVEL0 = 0,    
00630     IX_QMGR_Q_WM_LEVEL1 = 1,    
00631     IX_QMGR_Q_WM_LEVEL2 = 2,    
00632     IX_QMGR_Q_WM_LEVEL4 = 4,    
00633     IX_QMGR_Q_WM_LEVEL8 = 8,    
00634     IX_QMGR_Q_WM_LEVEL16 = 16,  
00635     IX_QMGR_Q_WM_LEVEL32 = 32,  
00636     IX_QMGR_Q_WM_LEVEL64 = 64   
00637 } IxQMgrWMLevel;
00638 
00651 typedef enum
00652 {
00653     IX_QMGR_QUELOW_GROUP = 0, 
00654     IX_QMGR_QUEUPP_GROUP      
00655 } IxQMgrDispatchGroup;
00656 
00668 typedef enum
00669 {
00670   IX_QMGR_Q_PRIORITY_0 = 0,  
00671   IX_QMGR_Q_PRIORITY_1,      
00672   IX_QMGR_Q_PRIORITY_2,      
00673   IX_QMGR_Q_PRIORITY_INVALID 
00674 } IxQMgrPriority;
00675 
00687 typedef unsigned IxQMgrCallbackId;
00688 
00699 typedef void (*IxQMgrCallback)(IxQMgrQId qId,
00700                                IxQMgrCallbackId cbId);
00701 
00714 typedef void (*IxQMgrDispatcherFuncPtr)(IxQMgrDispatchGroup group);
00715 
00716 /*
00717  * Function Prototypes
00718  */
00719 
00720 /* ------------------------------------------------------------
00721    Initialisation related functions
00722    ---------------------------------------------------------- */
00723 
00739 PUBLIC IX_STATUS
00740 ixQMgrInit (void);
00741 
00762 PUBLIC IX_STATUS
00763 ixQMgrUnload (void);
00764 
00778 PUBLIC void
00779 ixQMgrShow (void);
00780 
00797 PUBLIC IX_STATUS
00798 ixQMgrQShow (IxQMgrQId qId);
00799 
00800 
00801 /* ------------------------------------------------------------
00802    Configuration related functions
00803    ---------------------------------------------------------- */
00804 
00839 PUBLIC IX_STATUS
00840 ixQMgrQConfig (char *qName,
00841            IxQMgrQId qId,
00842            IxQMgrQSizeInWords qSizeInWords,
00843            IxQMgrQEntrySizeInWords qEntrySizeInWords);
00844 
00863 PUBLIC IX_STATUS
00864 ixQMgrQSizeInEntriesGet (IxQMgrQId qId,
00865              unsigned *qSizeInEntries);
00866 
00901 PUBLIC IX_STATUS
00902 ixQMgrWatermarkSet (IxQMgrQId qId,
00903             IxQMgrWMLevel ne,
00904             IxQMgrWMLevel nf);
00905 
00934 PUBLIC IX_STATUS
00935 ixQMgrAvailableSramAddressGet (UINT32 *address,
00936                    unsigned *sizeOfFreeSram);
00937 
00938 
00939 /* ------------------------------------------------------------
00940    Queue access related functions
00941    ---------------------------------------------------------- */
00942 
00970 PUBLIC IX_STATUS
00971 ixQMgrQReadWithChecks (IxQMgrQId qId,
00972                        UINT32 *entry);
00973 
00974 
00975 
00979 typedef struct
00980 {
00981     /* fields related to write functions */
00982     UINT32 qOflowStatBitMask;         
00983     UINT32 qWriteCount;               
00985     /* fields related to read and write functions */
00986     volatile UINT32 *qAccRegAddr;     
00987     volatile UINT32 *qUOStatRegAddr;  
00988     volatile UINT32 *qConfigRegAddr;  
00989     UINT32 qEntrySizeInWords;         
00990     UINT32 qSizeInEntries;            
00992     /* fields related to read functions */
00993     UINT32 qUflowStatBitMask;         
00994     UINT32 qReadCount;                
00995 } IxQMgrQInlinedReadWriteInfo;
00996 
00997 
01018 IX_STATUS
01019 ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
01020              UINT32 *entry);
01021 
01022 
01023 
01054 #ifdef NO_INLINE_APIS
01055 PUBLIC IX_STATUS
01056 ixQMgrQRead (IxQMgrQId qId,
01057              UINT32 *entryPtr);
01058 #else 
01059 extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
01060 extern IX_STATUS ixQMgrQReadMWordsMinus1 (IxQMgrQId qId, UINT32 *entryPtr);
01061 
01062 IX_QMGR_INLINE PUBLIC IX_STATUS
01063 ixQMgrQRead (IxQMgrQId qId,
01064              UINT32 *entryPtr);
01065 #endif
01066 
01067 IX_QMGR_INLINE PUBLIC IX_STATUS
01068 ixQMgrQRead (IxQMgrQId qId,
01069          UINT32 *entryPtr)
01070 #ifdef NO_INLINE_APIS
01071     ;
01072 #else
01073 {
01074     IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
01075     UINT32 entry, entrySize;
01076 
01077     /* get a new entry */
01078     entrySize = infoPtr->qEntrySizeInWords;
01079     entry = IX_OSSERV_READ_LONG(infoPtr->qAccRegAddr);
01080 
01081     if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
01082     {   
01083     *entryPtr = entry;
01084     /* process the remaining part of the entry */
01085     return ixQMgrQReadMWordsMinus1(qId, entryPtr);
01086     }
01087 
01088     /* underflow is available for lower queues only */
01089     if (qId < IX_QMGR_MIN_QUEUPP_QID)
01090     {
01091     /* the counter of queue entries is decremented. In happy 
01092      * day scenario there are many entries in the queue
01093      * and the counter does not reach zero.
01094      */
01095     if (infoPtr->qReadCount-- == 0)
01096     {
01097         /* There is maybe no entry in the queue
01098          * qReadCount is now negative, but will be corrected before
01099          * the function returns.
01100          */
01101         UINT32 qPtrs; /* queue internal pointers */
01102 
01103         /* when a queue is empty, the hw guarantees to return 
01104          * a null value. If the value is not null, the queue is
01105          * not empty.
01106          */
01107         if (entry == 0)
01108         {
01109         /* get the queue status */
01110         UINT32 status = IX_OSSERV_READ_LONG(infoPtr->qUOStatRegAddr);
01111     
01112         /* check the underflow status */
01113         if (status & infoPtr->qUflowStatBitMask)
01114         {
01115             /* the queue is empty 
01116             *  clear the underflow status bit if it was set 
01117             */
01118             IX_OSSERV_WRITE_LONG(infoPtr->qUOStatRegAddr,
01119                      status & ~infoPtr->qUflowStatBitMask);
01120             *entryPtr = 0;
01121             infoPtr->qReadCount = 0;
01122             return IX_QMGR_Q_UNDERFLOW;
01123         }
01124         }
01125         /* store the result */
01126         *entryPtr = entry;
01127 
01128         /* No underflow occured : someone is filling the queue
01129          * or the queue contains null entries.
01130          * The current counter needs to be
01131          * updated from the current number of entries in the queue
01132          */
01133 
01134         /* get snapshot of queue pointers */
01135         qPtrs = IX_OSSERV_READ_LONG(infoPtr->qConfigRegAddr);
01136 
01137         /* Mod subtraction of pointers to get number of words in Q. */
01138         qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; 
01139   
01140         if (qPtrs == 0)
01141         {
01142         /* no entry in the queue */
01143         infoPtr->qReadCount = 0;
01144         }
01145         else
01146         {
01147         /* convert the number of words inside the queue
01148          * to a number of entries 
01149          */
01150         infoPtr->qReadCount = qPtrs & (infoPtr->qSizeInEntries - 1);
01151         }
01152         return IX_SUCCESS;
01153     }
01154     }
01155     *entryPtr = entry;
01156     return IX_SUCCESS;
01157 }
01158 #endif
01159 
01206 #ifdef NO_INLINE_APIS  
01207 PUBLIC IX_STATUS
01208 ixQMgrQBurstRead (IxQMgrQId qId,
01209                   UINT32 numEntries,
01210                   UINT32 *entries);
01211 #else
01212 IX_QMGR_INLINE PUBLIC IX_STATUS
01213 ixQMgrQBurstRead (IxQMgrQId qId,
01214                   UINT32 numEntries,
01215                   UINT32 *entries);
01216 #endif  /* endif NO_INLINE_APIS */
01217 
01218 IX_QMGR_INLINE PUBLIC IX_STATUS
01219 ixQMgrQBurstRead (IxQMgrQId qId,
01220           UINT32 numEntries,
01221           UINT32 *entries)
01222 #ifdef NO_INLINE_APIS
01223 ;
01224 #else
01225 {
01226     IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
01227     UINT32 nullCheckEntry;
01228 
01229     if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
01230     {
01231     volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
01232 
01233     /* the code is optimized to take care of data dependencies:
01234      * Durig a read, there are a few cycles needed to get the 
01235      * read complete. During these cycles, it is poossible to
01236      * do some CPU, e.g. increment pointers and decrement 
01237      * counters.
01238      */
01239 
01240     /* fetch a queue entry */
01241     nullCheckEntry = IX_OSSERV_READ_LONG(infoPtr->qAccRegAddr);
01242 
01243     /* iterate the specified number of queue entries */ 
01244     while (--numEntries)
01245     {
01246         /* check the result of the previous read */
01247         if (nullCheckEntry == 0)
01248         {
01249         /* if we read a NULL entry, stop. We have underflowed */
01250         break;
01251         }
01252         else
01253         {
01254         /* write the entry */
01255         *entries = nullCheckEntry;
01256         /* fetch next entry */
01257         nullCheckEntry = IX_OSSERV_READ_LONG(qAccRegAddr);
01258         /* increment the write address */
01259         entries++;
01260         }
01261     }
01262     /* write the pre-fetched entry */
01263     *entries = nullCheckEntry;
01264     }
01265     else
01266     {
01267     IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
01268     /* read the specified number of queue entries */
01269     nullCheckEntry = 0;
01270     while (numEntries--)
01271     {
01272         UINT32 i;
01273 
01274         for (i = 0; i < entrySizeInWords; i++)
01275         {
01276         *entries = IX_OSSERV_READ_LONG(infoPtr->qAccRegAddr + i);
01277         nullCheckEntry |= *entries++;
01278         }
01279 
01280         /* if we read a NULL entry, stop. We have underflowed */
01281         if (nullCheckEntry == 0)
01282         {
01283         break;
01284         }
01285         nullCheckEntry = 0;
01286     }
01287     }
01288 
01289     /* reset the current read count : next access to the read function 
01290      * will force a underflow status check 
01291      */
01292     infoPtr->qReadCount = 0;
01293 
01294     /* Check if underflow occurred on the read */
01295     if (nullCheckEntry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID)
01296     {
01297     /* get the queue status */
01298     UINT32 status = IX_OSSERV_READ_LONG(infoPtr->qUOStatRegAddr);
01299 
01300     if (status & infoPtr->qUflowStatBitMask)
01301     {
01302         /* clear the underflow status bit if it was set */
01303         IX_OSSERV_WRITE_LONG(infoPtr->qUOStatRegAddr,
01304                  status & ~infoPtr->qUflowStatBitMask);
01305         return IX_QMGR_Q_UNDERFLOW;
01306     }
01307     }
01308 
01309     return IX_SUCCESS;
01310 }
01311 #endif
01312 
01339 IX_STATUS
01340 ixQMgrQPeek (IxQMgrQId qId,
01341          unsigned int entryIndex,
01342          UINT32 *entry);
01343 
01370 PUBLIC IX_STATUS
01371 ixQMgrQWriteWithChecks (IxQMgrQId qId,
01372                         UINT32 *entry);
01373 
01403 #ifdef NO_INLINE_APIS
01404 PUBLIC IX_STATUS
01405 ixQMgrQWrite (IxQMgrQId qId,
01406           UINT32 *entry);
01407 #else
01408 IX_QMGR_INLINE PUBLIC IX_STATUS
01409 ixQMgrQWrite (IxQMgrQId qId,
01410           UINT32 *entry);
01411 #endif /* NO_INLINE_APIS */
01412 
01413 IX_QMGR_INLINE PUBLIC IX_STATUS
01414 ixQMgrQWrite (IxQMgrQId qId,
01415           UINT32 *entry)
01416 #ifdef NO_INLINE_APIS
01417     ;
01418 #else
01419 {
01420     IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
01421     UINT32 entrySize;
01422 
01423     /* write the entry */
01424     IX_OSSERV_WRITE_LONG(infoPtr->qAccRegAddr, *entry);
01425     entrySize = infoPtr->qEntrySizeInWords;
01426 
01427     if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
01428     {   
01429     /* process the remaining part of the entry */
01430     volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
01431     while (--entrySize)
01432     {
01433         ++entry;
01434         IX_OSSERV_WRITE_LONG(++qAccRegAddr, *entry);
01435     }
01436     entrySize = infoPtr->qEntrySizeInWords;
01437     }
01438 
01439     /* overflow is available for lower queues only */
01440     if (qId < IX_QMGR_MIN_QUEUPP_QID)
01441     {   
01442     UINT32 qSize = infoPtr->qSizeInEntries;
01443     /* increment the current number of entries in the queue
01444      * and check for overflow 
01445      */
01446     if (infoPtr->qWriteCount++ == qSize)
01447     {
01448         /* the queue may have overflow */
01449         UINT32 qPtrs; /* queue internal pointers */
01450   
01451         /* get the queue status */
01452         UINT32 status = IX_OSSERV_READ_LONG(infoPtr->qUOStatRegAddr);
01453 
01454         /* read the status twice because the status may 
01455          * not be immediately ready after the write operation
01456          */
01457         if ((status & infoPtr->qOflowStatBitMask) ||
01458         ((status = IX_OSSERV_READ_LONG(infoPtr->qUOStatRegAddr))
01459          & infoPtr->qOflowStatBitMask))
01460         {
01461         /* the queue is full, clear the overflow status
01462          *  bit if it was set 
01463          */
01464         IX_OSSERV_WRITE_LONG(infoPtr->qUOStatRegAddr,
01465                      status & ~infoPtr->qOflowStatBitMask);
01466         infoPtr->qWriteCount = infoPtr->qSizeInEntries;
01467         return IX_QMGR_Q_OVERFLOW;
01468         }
01469         /* No overflow occured : someone is draining the queue
01470          * and the current counter needs to be
01471          * updated from the current number of entries in the queue
01472          */
01473 
01474         /* get q pointer snapshot */
01475         qPtrs = IX_OSSERV_READ_LONG(infoPtr->qConfigRegAddr);
01476 
01477         /* Mod subtraction of pointers to get number of words in Q. */
01478         qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; 
01479 
01480         if (qPtrs == 0)
01481         {
01482         /* the queue may be full at the time of the 
01483          * snapshot. Next access will check 
01484          * the overflow status again.
01485          */
01486         infoPtr->qWriteCount = qSize;
01487         }
01488         else 
01489         {
01490         /* convert the number of words to a number of entries */
01491         if (entrySize == IX_QMGR_Q_ENTRY_SIZE1)
01492         {
01493             infoPtr->qWriteCount = qPtrs & (qSize - 1);
01494         }
01495         else
01496         {
01497             infoPtr->qWriteCount = (qPtrs / entrySize) & (qSize - 1);
01498         }
01499         }
01500     }
01501     }
01502     return IX_SUCCESS;
01503 }
01504 #endif
01505 
01548 #ifdef NO_INLINE_APIS
01549 PUBLIC IX_STATUS
01550 ixQMgrQBurstWrite (IxQMgrQId qId,
01551            unsigned numEntries,
01552            UINT32 *entries);
01553 #else
01554 IX_QMGR_INLINE PUBLIC IX_STATUS
01555 ixQMgrQBurstWrite (IxQMgrQId qId,
01556            unsigned numEntries,
01557            UINT32 *entries);
01558 #endif /* NO_INLINE_APIS */
01559 
01560 IX_QMGR_INLINE PUBLIC IX_STATUS
01561 ixQMgrQBurstWrite (IxQMgrQId qId,
01562            unsigned numEntries,
01563            UINT32 *entries)
01564 #ifdef NO_INLINE_APIS
01565 ;
01566 #else
01567 {
01568     IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
01569     UINT32 status;
01570 
01571     /* update the current write count */
01572     infoPtr->qWriteCount += numEntries;
01573 
01574     if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
01575     {
01576     volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
01577     while (numEntries--)
01578     {
01579         IX_OSSERV_WRITE_LONG(qAccRegAddr, *entries);
01580         entries++;
01581     }
01582     }
01583     else
01584     {
01585     IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
01586     UINT32 i;
01587 
01588     /* write each queue entry */
01589     while (numEntries--)
01590     {
01591         /* write the queueEntrySize number of words for each entry */
01592         for (i = 0; i < entrySizeInWords; i++)
01593         {
01594         IX_OSSERV_WRITE_LONG((infoPtr->qAccRegAddr + i), *entries);
01595         entries++;
01596         }
01597     }
01598     }
01599 
01600     /* check if the write count overflows */
01601     if (infoPtr->qWriteCount > infoPtr->qSizeInEntries)
01602     {
01603     /* reset the current write count */
01604     infoPtr->qWriteCount = infoPtr->qSizeInEntries;
01605     }
01606 
01607     /* Check if overflow occurred on the write operation */
01608     if (qId < IX_QMGR_MIN_QUEUPP_QID)
01609     {
01610     /* get the queue status */
01611     status = IX_OSSERV_READ_LONG(infoPtr->qUOStatRegAddr);
01612 
01613     /* read the status twice because the status may 
01614      * not be ready at the time of the write
01615      */
01616     if ((status & infoPtr->qOflowStatBitMask) ||
01617         ((status = IX_OSSERV_READ_LONG(infoPtr->qUOStatRegAddr))
01618          & infoPtr->qOflowStatBitMask))
01619     {
01620         /* clear the underflow status bit if it was set */
01621         IX_OSSERV_WRITE_LONG(infoPtr->qUOStatRegAddr,
01622                  status & ~infoPtr->qOflowStatBitMask);
01623         return IX_QMGR_Q_OVERFLOW;
01624     }
01625     }
01626 
01627     return IX_SUCCESS;
01628 }
01629 #endif
01630 
01657 IX_STATUS
01658 ixQMgrQPoke (IxQMgrQId qId,
01659          unsigned int entryIndex,
01660          UINT32 *entry);
01661 
01682 PUBLIC IX_STATUS
01683 ixQMgrQNumEntriesGet (IxQMgrQId qId,
01684               unsigned *numEntries);
01685 
01707 PUBLIC IX_STATUS
01708 ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
01709                             IxQMgrQStatus *qStatus);
01710 
01737 #ifdef NO_INLINE_APIS
01738 PUBLIC IX_STATUS
01739 ixQMgrQStatusGet (IxQMgrQId qId,
01740           IxQMgrQStatus *qStatus);
01741 #else  
01742 extern UINT32 ixQMgrAqmIfQueLowStatRegAddr[];
01743 extern UINT32 ixQMgrAqmIfQueLowStatBitsOffset[];
01744 extern UINT32 ixQMgrAqmIfQueLowStatBitsMask;
01745 extern UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
01746 extern UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
01747 extern UINT32 ixQMgrAqmIfQueUppStat0BitMask[];
01748 extern UINT32 ixQMgrAqmIfQueUppStat1BitMask[];
01749 
01750 IX_QMGR_INLINE PUBLIC IX_STATUS
01751 ixQMgrQStatusGet (IxQMgrQId qId,
01752           IxQMgrQStatus *qStatus);
01753 #endif  /* endif NO_INLINE_APIS */
01754 
01755 IX_QMGR_INLINE PUBLIC IX_STATUS
01756 ixQMgrQStatusGet (IxQMgrQId qId,
01757           IxQMgrQStatus *qStatus)
01758 #ifdef NO_INLINE_APIS
01759     ;
01760 #else
01761 {
01762     /* read the status of a queue in the range 0-31 */
01763     if (qId < IX_QMGR_MIN_QUEUPP_QID)
01764     {
01765     volatile UINT32 *lowStatRegAddr = (UINT32*)ixQMgrAqmIfQueLowStatRegAddr[qId];
01766 
01767     UINT32 lowStatBitsOffset = ixQMgrAqmIfQueLowStatBitsOffset[qId];
01768     UINT32 lowStatBitsMask   = ixQMgrAqmIfQueLowStatBitsMask;
01769 
01770     /* read the status register for this queue */
01771     *qStatus = IX_OSSERV_READ_LONG(lowStatRegAddr);
01772 
01773     /* mask out the status bits relevant only to this queue */
01774     *qStatus = (*qStatus >> lowStatBitsOffset) & lowStatBitsMask;
01775 
01776     }
01777     else /* read status of a queue in the range 32-63 */
01778     {
01779 
01780     volatile UINT32 *qNearEmptyStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat0RegAddr;
01781     volatile UINT32 *qFullStatRegAddr      = (UINT32*)ixQMgrAqmIfQueUppStat1RegAddr;
01782     int maskIndex = qId - IX_QMGR_MIN_QUEUPP_QID;
01783     UINT32 qNearEmptyStatBitMask = ixQMgrAqmIfQueUppStat0BitMask[maskIndex];
01784     UINT32 qFullStatBitMask      = ixQMgrAqmIfQueUppStat1BitMask[maskIndex];
01785 
01786     /* Reset the status bits */
01787     *qStatus = 0;
01788 
01789     /* Check if the queue is nearly empty */
01790     if (IX_OSSERV_READ_LONG(qNearEmptyStatRegAddr) & qNearEmptyStatBitMask)
01791     {
01792         *qStatus |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
01793     }
01794 
01795     /* Check if the queue is full */
01796     if (IX_OSSERV_READ_LONG(qFullStatRegAddr) & qFullStatBitMask)
01797     {
01798         *qStatus |= IX_QMGR_Q_STATUS_F_BIT_MASK;
01799     }
01800     }
01801     return IX_SUCCESS;
01802 }
01803 #endif
01804 
01805 /* ------------------------------------------------------------
01806    Queue dispatch related functions
01807    ---------------------------------------------------------- */
01808 
01832 PUBLIC IX_STATUS
01833 ixQMgrDispatcherPrioritySet (IxQMgrQId qId,
01834                  IxQMgrPriority priority);
01866 PUBLIC IX_STATUS
01867 ixQMgrNotificationEnable (IxQMgrQId qId,
01868               IxQMgrSourceId sourceId);
01869 
01887 PUBLIC IX_STATUS
01888 ixQMgrNotificationDisable (IxQMgrQId qId);
01889 
01931 PUBLIC void
01932 ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group);
01933 
01981 PUBLIC void
01982 ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group);
01983 
02007 PUBLIC IX_STATUS
02008 ixQMgrNotificationCallbackSet (IxQMgrQId qId,
02009                    IxQMgrCallback callback,
02010                    IxQMgrCallbackId callbackId);
02011 
02027 PUBLIC void
02028 ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr);
02029 
02050 PUBLIC void
02051 ixQMgrStickyInterruptRegEnable(void);
02052 
02053 
02054 /* Restore IX_COMPONENT_NAME */
02055 #undef IX_COMPONENT_NAME
02056 #define IX_COMPONENT_NAME IX_QMGR_SAVED_COMPONENT_NAME
02057 
02058 #endif /* IXQMGR_H */
02059 
Automatically generated from sources. © Intel Corp. 2003